TI中文支持网Hello,
I am attempting to write a linux driver to interface with another CPU using McBSP3 by poll writing. To do this, I need the McBSP to supply both clock and frame-sync signals and output to the outside-connected CPU.
The problem is that transmit appears to be not functional since there is nothing on DX pin. We can have the CLKX output and see clearly on scope, but the XBUFFSTAT is always empty even we write 16 bits data into DXR1 all the time. And since FSGM is set to 0(only transmit when XB is not empty), so there is no any signals on FSX and DX pin. (we also did some test, if FSGM=1, FSX will be generated automatically, but the data on DX is always 0)
Normally when data is wrote into DXR, it will be copied into transmit buffer(XB) automatically, and then FSX will be generated, data will be shifted into XSR then to DX pin.
It is really confuing issue and we have checked the register configuration for several times, no any clue!
Any help would be appreciated! Thanks!
// Initialize McBSP
memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); // Set all register values to zero before configuration.
mcbsp_cfg.spcr2 |= FREE;
mcbsp_cfg.rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
mcbsp_cfg.rcr1 |= RFRLEN1(0); // Set frame length to 1 word. For more channels, this number will increase
mcbsp_cfg.rcr2 |= RDATDLY(1); //1-bit data delay, so the FSR length is 1-clock
mcbsp_cfg.xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
mcbsp_cfg.xcr1 |= XFRLEN1(0); //set frame length to 1 word
mcbsp_cfg.xcr2 |= XDATDLY(1); //1-bit data delay for transmit, so FSX length is 1-clock
mcbsp_cfg.srgr1 |= FWID(0); //the frame width is 1-clock
mcbsp_cfg.srgr1 |= CLKGDV(31);//the internal clock is 48MHz, so here divider should be 16 to generate 3MHz.
mcbsp_cfg.srgr2 |= CLKSM; //SRG clock derived from the McBSPi_ICLK
mcbsp_cfg.srgr2 |= FPER(20); //the period of frame is 21 clocks,
//mcbsp_cfg.srgr2 |= FSGM;
mcbsp_cfg.pcr0 |= FSXM; //Frame synchronization is determined by FSGM in SRGR2,output
//mcbsp_cfg.pcr0 |= FSRM;
mcbsp_cfg.pcr0 |= CLKXM;//CLKX is an output pin and is drivern by internal SRG.
//mcbsp_cfg.pcr0 |= CLKRM;
mcbsp_cfg.mcr1 |= RMCME_ATOH;
mcbsp_cfg.mcr2 |= XMCME_ATOH;
mcbsp_cfg.mcr2 |= XMCM(0x01);
mcbsp_cfg.rcera |= 0x01;
mcbsp_cfg.xcera |= 0x01;
status = omap_mcbsp_set_io_type(FE_BOARD_MCBSP_ID, OMAP_MCBSP_POLL_IO);
if(status)
{
printk(KERN_ERR "Error: Could not configure McBSP3. Error Code: %d.\n", status);
return -1;
}
printk("fe_board_init_mcbsp: omap_mcbsp_set_io_type OK\n");
status = omap_mcbsp_request(FE_BOARD_MCBSP_ID);
if(status)
{
printk(KERN_ERR "Error: Could not request McBSP3. Error Code: %d.\n", status);
return -1;
}
printk("fe_board_init_mcbsp: omap_mcbsp_request OK\n");
omap_mcbsp_config(FE_BOARD_MCBSP_ID, &mcbsp_cfg); // Configures the McBSP registers
printk("fe_board_init_mcbsp: omap_mcbsp_config\n");
omap_mcbsp_enable_clks(FE_BOARD_MCBSP_ID);
printk("fe_board_init_mcbsp: omap_mcbsp_enable_clks\n");
// enable transmitter
omap_mcbsp_start(FE_BOARD_MCBSP_ID, 1, 1);
printk("fe_board_init_mcbsp: omap_mcbsp_start\n");
william li2：
The macro FE_BOARD_MCBSP_ID is 2.
william li2：
回复 william li2:
And for write, function omap_mcbsp_pollwrite() is called.
