TI中文支持网我用GMPC+DM9000外扩一路网口，用的是GPMC_A0，数据位是16位，用的是CS1，配置如下：
{
int cs = 1; /* Chip Select on GPMC bus */
int val;
if (gpmc_cs_request(cs, SZ_16M, &cpld_gpmc_mem_base_phys) < 0) {
printk(KERN_ERR "[ext_uart platform init]: gpmc_cs_request failed\n");
return -1;
}
// printk(KERN_INFO "qianyd %x\n", cpld_gpmc_mem_base_phys);
if (gpmc_cs_configure(cs, GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NOR) < 0) {
printk(KERN_ERR "[ext_uart platform init]: gpmc_cs_configure failed\n");
return -1;
}
// val = GPMC_CONFIG1_READMULTIPLE_SUPP;
val = GPMC_CONFIG1_READTYPE_SYNC;
val |= GPMC_CONFIG1_WRITETYPE_SYNC;
// val |= GPMC_CONFIG1_CLKACTIVATIONTIME(2);
// val |= GPMC_CONFIG1_PAGE_LEN(2);
// val |= GPMC_CONFIG1_DEVICESIZE(0); /* 8-bit */
// val |= GPMC_CONFIG1_DEVICETYPE_NOR;
// val |= GPMC_CONFIG1_MUXADDDATA;
// val |= GPMC_CONFIG1_WAIT_READ_MON;
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, val);
if (gpmc_cs_set_timings(cs, &ext_uart_timings) < 0) {
printk(KERN_ERR "Failed gpmc_cs_set_timings for ST16C554 device\n");
goto free;
}
#if 0
val = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG6);
val &= 0xe0000000;
val |= ((1<<7)|(2<<8)|(3<<24)| 30);
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG6, val);
#endif
printk(KERN_INFO "gpmc_cssp_init for ST16C554 device succeeded\n");
return 0;
free:
gpmc_cs_free(cs);
printk(KERN_ERR "Could not initialize ST16C554 device\n");
return -1;
}
时序配置如下：
{
/* Minimum clock period for synchronous mode (in picoseconds) */
.sync_clk = 0,
/* CS signal timings corresponding to GPMC_CONFIG2 */
.cs_on = 10, /* T6s */
.cs_rd_off = 85, /* oe_off + T7h */
.cs_wr_off = 60, /* Tcs for write: we_off + T13h */
/* ADV signal timings corresponding to GPMC_CONFIG3 */
// .adv_on = 0, /* Address setup Tas*/
// .adv_rd_off = 110, /* Read deassertion time Trd + Tdd*/
// .adv_wr_off = 90, /* Write deassertion time Twr + Tdh*/
/* WE signals timings corresponding to GPMC_CONFIG4 */
.we_on = 20, /* WE assertion time: cs_on + T13d */
.we_off = 60, /* WE deassertion time: we_on + T13w */
/* OE signals timings corresponding to GPMC_CONFIG4 */
.oe_on = 25, /* OE assertion time: cs_on + T7d */
.oe_off = 75, /* OE deassertion time: oe_on + T7w */
/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
// .page_burst_access = 2 * 10, /* Multiple access word delay */
.access = 65, /* Start-cycle to first data valid delay: at leaset oe_on + T12d */
.rd_cycle = 115, /* Total read cycle time: cs_rd_off + (T9d – T7h) – oe_on */
.wr_cycle = 90, /* Total write cycle time: cs_wr_off + (T15d – T13h) – we_on */
/* The following are only on OMAP3430 */
.wr_access = 40, /* WRACCESSTIME: max we_off – T16s */
.wr_data_mux_bus = 0, /* WRDATAONADMUXBUS */
}
出现的问题如下：
[ 5.638735] dm9000 dm9000: read wrong id 0x2b2a2928
[ 5.643839] dm9000 dm9000: read wrong id 0x2b2a2928
[ 5.648956] dm9000 dm9000: read wrong id 0x2b2a2928
[ 5.654056] dm9000 dm9000: read wrong id 0x2b2a2928
[ 5.659165] dm9000 dm9000: read wrong id 0x2b2a2928
[ 5.664265] dm9000 dm9000: read wrong id 0x2b2a2928
[ 5.669372] dm9000 dm9000: read wrong id 0x2b2a2928
[ 5.674472] dm9000 dm9000: read wrong id 0x2b2a2928
这个问题是我的配置或者时序的配置问题吗？
Steven Liu1：
不用贴这么多code，意义不大，对于找问题没啥帮助。建议排查以下几点：
1. GPMC和DM9000的对接方式。在硬件设计上是不是数据线和地址线分开的？还是复用的？这个会直接决定了你对于GPMC_CONFIG0寄存器的一些位的设置。
2. GPMC本身的memory map的规划。我有点印象的是貌似DM9000是当做nor flash like device的方式来处理的，所以你要为他分配一个地址空间，这个地址空间一要够用，二不能出现和其他片选空间的重叠。更细节的，可以参考我以前写过的一个地址区域划分的文件：http://www.deyisupport.com/files/m/sitara_arm/11905.aspx
3. 时序上的配置，这个要看DM9000手册的要求和AM335x的TRM手册相关章节，确保你的DM9K是可以正常被访问的。建议你先自己配一下，试试看，如果排查其他的问题，还是在这块有疑虑，把DM9000的要求时序和你的GPMC对应配置的时序发上来，可以一起鉴别。
最后，以前写过的一个小例程，是裸机的，当时是为了引导大家去写和FPGA通信的，也可以作为DM9K的参考：
http://www.deyisupport.com/files/m/sitara_arm/11906.aspx
