TI中文支持网AM3354 +LAN8720 以太网调试一直调试不通，u-boot是2014.7月版本。采用RMII接口，目前网口灯不闪，示波器检测REFCLKO引脚无波形输出！
板子是自己画的 上面有两个网卡 目前只调了一个网口！
/u-boot-2014.07/board/ti/am335x中 mux.c
添加：
static struct module_pin_mux rmii1_pin_mux[] = {
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
// {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
{-1},
};
修改： enable_board_pin_mux函数
void enable_board_pin_mux(struct am335x_baseboard_id *header)
{
/* Do board-specific muxes. */
/* Beaglebone pinmux */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(rmii1_pin_mux);
//configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#ifndef CONFIG_NOR
configure_module_pin_mux(mmc1_pin_mux);
#endif
#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
configure_module_pin_mux(bone_norcape_pin_mux);
#endif
}
修改/u-boot-2014.07/board/ti/am335x中 board.c
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
__maybe_unused struct am335x_baseboard_id header;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#ifdef CONFIG_DRIVER_TI_CPSW
mac_lo = readl(&cdev->macid1l);
mac_hi = readl(&cdev->macid1h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!getenv("eth1addr")) {
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
if (board_is_bone(&header) || board_is_bone_lt(&header) ||
board_is_idk(&header)) {
puts("\nMII_MODE_ENABLE is selected!\n");
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else {
puts("\nRMII_MODE_ENABLE is selected!\n");
writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
cpsw_slaves[0].phy_if = //cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RMII;
//writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
//cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
// PHY_INTERFACE_MODE_RGMII;
}
// bsp_dump_net_reg();
rv = cpsw_register(&cpsw_data);
// bsp_dump_net_reg();
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
/*
*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the AR8051 PHY. Since we only support a single ethernet
* device in U-Boot, we only do this for the first instance.
*/
/*
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
const char *devname;
devname = miiphy_get_current_dev();
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
AR8051_DEBUG_RGMII_CLK_DLY_REG);
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
AR8051_RGMII_TX_CLK_DLY);
}
*/
#endif
return n;
}
修改 arc\arm\dts 下am335x-bone-common.dtsi文件
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
//0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
//0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
//0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
//0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
0x144 (0x20 | 0x01) /* rmii1_refclk.rmii1_refclk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
//0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
//0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
//0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
//0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
dual_emac_res_vlan = <2>;
phy-mode = "rmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
dual_emac_res_vlan = <3>;
phy-mode = "rmii";
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac;
status = "okay";
};
下载的u-boot是采用的mii目前要做成RMII的 不知道问题处在什么地方，有人给指导一下吗？？、
或者谁有相关移植说明发一份谢谢！邮箱地址：lijun10210@163.com
Shine：
看一下是否用了外部晶振，小于或等于50ppm，GMII_SEL寄存器要配置成RMII mode。请看下面errata的说明Advisory 1.0.16。
www.ti.com/…/sprz360i.pdf
