AM5708 怎么在dsp1中初始化mcasp8，有没有文档或者示例

论坛的专家大家好：

我们公司使用的是一块创龙的开发版，只有mcasp8接口引出来了。我们想要使用这个接口输出音频。希望延迟1ms左右。

目前我已经把ti在mcasp模块的5728的示例代码跑起来了，但是示例代码使用的是mcasp3，我把mcasp3都替换成mcasp8结果程序就在下面的代码死循环了。

我想请教一下，有没有关于mcasp8初始化的示例或者更详细的文档。
    status = mcaspCreateChan(&hMcaspTxChan, hMcaspDev,
                             MCASP_OUTPUT,
                             &mcasp_chanparam[1],
                             mcaspAppCallback, NULL);

谢谢

Nancy Wang：

请问是参考的那个示例代码？
具体配置流程可以参考TRM：24.6.5 McASP Low-Level Programming Model
www.ti.com/…/spruhz6l.pdf
要替换引脚一般要注意pinmux的配置问题，请先结合pinmux工具看一下引脚复用配置有没有问题。
www.ti.com/…/PINMUXTOOL

Q L：

回复 Nancy Wang:

工程是：C:\ti\pdk_am57xx_1_0_10\packages\ti\drv\mcasp\example\evmAM572x\c66\bios\project\MCASP_Audio_evmAM572x_c66ExampleProject_c66
你能看一下我改的这个函数有没有问题吗？

void McASP3_Enable(void)
{
//uint32_t regVal = 0U;
// Choose SYS_CLK2 (22.5792 MHZ) as source for ABE_PLL REF CLKHW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG, \CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL, \CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK2);
/* Reprogram ABE DPLL for 451.584 MHz output on PER_ABE_X1_GFCLK line */
// step 1: disable the PLL, if enabled (ex: via GEL)while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) == CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_FR_BYP_MODE);
// step 2: modify Synthesized Clock Parameters – DPLL MULT & DIVHW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT, \0xC8);
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV, \0x09);
// step 3: Configure output clocks parameters – M2 = 1M3 = 1HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS, \0x1);HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS, \0x1);
// step 4: Confirm that the PLL has lockedwhile(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) != CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE);
/* McASP3 Module Control */HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG, \CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG_MODULEMODE, \CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG_MODULEMODE_ENABLE);while (HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG) != \CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG_MODULEMODE_ENABLE) ;

/* PAD IO Config for McASP3 pins – ACLKX, AFSX, AXR0, AXR1*/
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR4, \CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR4_MCASP2_AXR4_MUXMODE, \0x1);HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR7, \CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR7_MCASP2_AXR7_MUXMODE, \0x1);HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR6, \CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR6_MCASP2_AXR6_MUXMODE, \0x1);HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR5, \CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR5_MCASP2_AXR5_MUXMODE, \0x1);//HW_WR_REG32(0x4AE06160, 0x1); // CM_CLKSEL_CLKOUT2: 0x1: Selects SYS_CLK2HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG, \CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL, \CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_SYS_CLK2);
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_INPUTENABLE, \0x0); // 0x0: Receive mode is disabled
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_MUXMODE, \0x9); //0x9: clkout2
HW_WR_FIELD32(CSL_DSP_COREAON_CM_CORE_REGS+CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG, \CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK, \CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK_FCLK_EN);

}

Nancy Wang：

回复 Q L:

建议将修改过的部分标红一下发上来。

另外建议可以先写一个小的测试程序，看一下配置后的的引脚能否正常翻转。

再做一下回环自测看一下是否有问题。

Q L：

回复 Nancy Wang:

void McASP3_Enable(void) { //uint32_t regVal = 0U; // Choose SYS_CLK2 (22.5792 MHZ) as source for ABE_PLL REF CLK HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG, \ CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL, \ CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK2); /* Reprogram ABE DPLL for 451.584 MHz output on PER_ABE_X1_GFCLK line */ // step 1: disable the PLL, if enabled (ex: via GEL) while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) == CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE) HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \ CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_FR_BYP_MODE); // step 2: modify Synthesized Clock Parameters – DPLL MULT & DIV HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT, \ 0xC8); HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV, \ 0x09); // step 3: Configure output clocks parameters – M2 = 1 M3 = 1 HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS, \ 0x1); HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS, \ 0x1); // step 4: Confirm that the PLL has locked while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) != CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE) HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \ CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \ CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE); /* McASP3 Module Control */ HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG, \ CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG_MODULEMODE, \ CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG_MODULEMODE_ENABLE); while (HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG) != \ CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP8_CLKCTRL_REG_MODULEMODE_ENABLE) ; /* PAD IO Config for McASP3 pins – ACLKX, AFSX, AXR0, AXR1*/ HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR4, \ CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR4_MCASP2_AXR4_MUXMODE, \ 0x1); HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR7, \ CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR7_MCASP2_AXR7_MUXMODE, \ 0x1); HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR6, \ CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR6_MCASP2_AXR6_MUXMODE, \ 0x1); HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR5, \ CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR5_MCASP2_AXR5_MUXMODE, \ 0x1); //HW_WR_REG32(0x4AE06160, 0x1); // CM_CLKSEL_CLKOUT2: 0x1: Selects SYS_CLK2 HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG, \ CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL, \ CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_SYS_CLK2); HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \ CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_INPUTENABLE, \ 0x0); // 0x0: Receive mode is disabled HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \ CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_MUXMODE, \ 0x9); //0x9: clkout2 HW_WR_FIELD32(CSL_DSP_COREAON_CM_CORE_REGS+CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG, \ CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK, \ CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK_FCLK_EN); }

这段代码我只修改了上面标红的部分，分别是配置关闭mcasp8和mcasp8输出管脚的代码，你看下是否还要修改其他的地方呢？