DM6467平台关于CE Server端groupId配置问题

感谢您的解答！

我们在开发过程中使用了H264的编解码算法，开始时我们将编解码算法配置在了相同的groupID内，长时间运行后会导致dsp端崩溃，通过编解码加锁，情况会明显改善，故我们考虑是资源共享出了问题，于是尝试配置编解码算法在不同的group内，但是按照示例配置，不同group后，编码算法总是创建失败，由于对这方面的配置不是很熟悉，所以也不知道哪里没有配置正确，下面是配置文件内容

/* set up OSAL */

var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');

osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;

osalGlobal.traceBufferSize = 0x40000;

/* configure default memory seg id to BIOS-defined "DDR" */

osalGlobal.defaultMemSegId = "DDR2";

osalGlobal.embedBuildInfo = false;

/* Enable DSP-side BIOS logging */

var LogServer = xdc.useModule('ti.sdo.ce.bioslog.LogServer');

/*

*  ======== Server Configuration ========

*/

var Server = xdc.useModule('ti.sdo.ce.Server');

Server.threadAttrs.stackSize = 16384;

/* The servers execution priority */

Server.threadAttrs.priority = Server.MINPRI;

/*

* The optional stack pad to add to non-configured stacks.  This is well

* beyond most codec needs, but follows the approach of "start big and

* safe, then optimize when things are working."

*/

Server.stackSizePad = 9000;

/* get various codec modules; i.e., implementation of codecs */

var H264HDENC = xdc.useModule('ti.sdo.codecs.h264hdenc.ce.H264HDENC');

//    H264HDENC.manageInBufsCache = [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ];

   H264HDENC.manageOutBufsCache = [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ];

   H264HDENC.alg.codeSection = "DDR2";

//   H264HDENC.alg.udataSection = "DDR2";

//   H264HDENC.alg.dataSection = "DDR2";

var H264DEC = xdc.useModule('ti.sdo.codecs.h264dec.ce.H264DEC');

H264DEC.alg.watermark      = false; /*if it is production version.*/

// H264DEC.manageInBufsCache =  [ true, true, true,true, true,true, true, true, true, true, true, true, true, true, true,true];

// H264DEC.manageOutBufsCache = [ true, true, true,true, true,true, true, true, true, true, true, true, true, true, true, true ];

H264DEC.alg.codeSection  = "DDR2";

// H264DEC.alg.udataSection = "DDRALGHEAP";//"DDR2";

// H264DEC.alg.dataSection = "DDRALGHEAP";//"DDR2";

var HDVICP = xdc.useModule('ti.sdo.codecs.hdvicp.HDVICP');

var AACHEENC = xdc.useModule('ti.sdo.codecs.aacheenc.ce.AACHEENC');

   AACHEENC.alg.watermark = false;

   AACHEENC.alg.codeSection = "DDR2";

   AACHEENC.alg.udataSection = "DDR2";

   AACHEENC.alg.dataSection = "DDR2";

var MP3DEC = xdc.useModule('ti.sdo.codecs.mp3dec.ce.MP3DEC');

   MP3DEC.alg.watermark = false;

   MP3DEC.alg.codeSection = "DDR2";

   MP3DEC.alg.udataSection = "DDR2";

   MP3DEC.alg.dataSection = "DDR2";

var IMGENC1_DEINTERLACE = xdc.useModule('ti.sdo.codecs.imgenc1_deinterlace.IMGENC1_DEINTERLACE');

var IMGENC1_OSD = xdc.useModule('ti.sdo.codecs.imgenc1_osd.IMGENC1_OSD');

var IMGENC1_CHECK = xdc.useModule('ti.sdo.codecs.imgenc1_check.IMGENC1_CHECK');

var IMGENC1_COPY = xdc.useModule('ti.sdo.codecs.imgenc1_copy.IMGENC1_COPY');

var COLORBARCHECK = xdc.useModule('ti.sdo.codecs.colorbarcheck.COLORBARCHECK');

Server.algs = [

   {name: "h264hdenc", mod: H264HDENC,groupId:0,threadAttrs: {

stackMemId: 0, priority: Server.MINPRI + 1}

   },  

   {name: "h264dec", mod: H264DEC,groupId:1,threadAttrs: {

        stackMemId: 0, priority: Server.MINPRI + 3}

   },    

   {name: "aacheenc", mod: AACHEENC,groupId:2,threadAttrs: {

stackMemId: 0, priority: Server.MINPRI + 2}

   },

   {name: "imgenc1_deinterlace", mod: IMGENC1_DEINTERLACE,groupId:2,threadAttrs: {

stackMemId: 0, priority: Server.MINPRI + 1}

   },

   {name: "imgenc1_osd", mod: IMGENC1_OSD,groupId:2,threadAttrs: {

stackMemId: 0, priority: Server.MINPRI + 2}

   },

   {name: "imgenc1_copy", mod: IMGENC1_COPY,groupId:2,threadAttrs: {

   stackMemId: 0, priority: Server.MINPRI + 2}

   },

   {name: "imgenc1_check", mod: IMGENC1_CHECK,groupId:2,threadAttrs: {

stackMemId: 0, priority: Server.MINPRI + 2}

   },

   {name: "colorbarcheck", mod: COLORBARCHECK,groupId:2,threadAttrs: {

   stackMemId: 0, priority: Server.MINPRI + 2}

   },

];

/*

*  ======== DSKT2 and RMAN Configuration ========

*  XDAIS Algorithm Memory and DMA allocation

*/

   var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');

   DSKT2.DARAM0     = "IRAM";

   DSKT2.DARAM1     = "IRAM";

   DSKT2.DARAM2     = "IRAM";

   DSKT2.SARAM0     = "L1DHEAP";

   DSKT2.SARAM1     = "L1DHEAP";

   DSKT2.SARAM2     = "L1DHEAP";

   DSKT2.ESDATA     = "DDRALGHEAP";

   DSKT2.IPROG      = "DDRALGHEAP";//"IRAM";

   DSKT2.EPROG      = "DDRALGHEAP";//"DDR2";

   DSKT2.DSKT2_HEAP = "DDRALGHEAP";//"DDR2";    /* to allocate internal DSKT2 object */

   // DSKT2.trace = true;

   // DSKT2.debug = false;

   /* Scratch group 0 */

   // DSKT2.DARAM_SCRATCH_SIZES = [64*1024,64*1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];

    // DSKT2.SARAM_SCRATCH_SIZES = [64*1024,64*1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];

DSKT2.DARAM_SCRATCH_SIZES[0] = 64*1024;

  DSKT2.SARAM_SCRATCH_SIZES[0] = 64*1024;

   // /* Scratch group 1 */

  DSKT2.DARAM_SCRATCH_SIZES[1] = 64*1024;

  DSKT2.SARAM_SCRATCH_SIZES[1] = 64*1024;

   var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');

   RMAN.useDSKT2 = true;

   RMAN.tableSize = 10;

   RMAN.semCreateFxn = "Sem_create";

   RMAN.semDeleteFxn = "Sem_delete";

   RMAN.semPendFxn = "Sem_pend";

   RMAN.semPostFxn = "Sem_post";

   RMAN.debug = false;

   RMAN.trace = true;    

   var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');

   DMAN3.heapInternal    = "L1DHEAP"; //"IRAM";       /* L1DHEAP is an internal segment */

   DMAN3.heapExternal    = "DDRALGHEAP";    /* DDRALGHEAP is an external segment */

   DMAN3.idma3Internal   = false;

   DMAN3.scratchAllocFxn = "DSKT2_allocScratch";

   DMAN3.scratchFreeFxn  = "DSKT2_freeScratch";

   var EDMA3 = xdc.useModule('ti.sdo.fc.edma3.Settings');    

   EDMA3.trace = true;

   EDMA3.debug = false;      

   //EDMA3.regionConfig = "DM6467_EDMA3_RM_INITCONFIG";

   /*

    *

    * Group:0, H264ENC gets 192 PaRAMs, 13 TCCs, 19 EDMA, and 2 QDMA channels

    */

// DMAN3.numTccGroup   = [22, 22, 0, 0, 0, 0];

// DMAN3.numPaRamGroup = [93, 192, 0, 0, 0, 0];

// DMAN3.qdmaChannels = [0, 2, 0, 0, 0, 0, 0,0];

// DMAN3.maxQdmaChannels = 8;

// DMAN3.numQdmaChannels = 8;

   // EDMA3.maxPaRams[0] = 384;

   // EDMA3.maxTccs[0] = 49;//21;

   // EDMA3.maxEdmaChannels[0] = 49;//21;

   // EDMA3.maxQdmaChannels[0] = 4;

EDMA3.maxPaRams[0] = 93;

   EDMA3.maxTccs[0] = 22;//21;

   EDMA3.maxEdmaChannels[0] = 22;//21;

   EDMA3.maxQdmaChannels[0] = 0;

    /*

    * Group:1, H264DEC gets 192 PaRAMs, 13 TCCs, 19 EDMA, and 2 QDMA channels

    */

  // EDMA3.maxPaRams[1] = 93;

  // EDMA3.maxTccs[1] = 22;

  // EDMA3.maxEdmaChannels[1] = 22;

  // EDMA3.maxQdmaChannels[1] = 0;

   EDMA3.maxPaRams[1] = 192;

   EDMA3.maxTccs[1] = 22;

   EDMA3.maxEdmaChannels[1] = 22;

   EDMA3.maxQdmaChannels[1] = 2;

   var EDMA3CHAN = xdc.useModule('ti.sdo.fc.ires.edma3chan.EDMA3CHAN');

   EDMA3CHAN.debug = false;

   EDMA3CHAN.trace = true;

   var HDVICP =  xdc.useModule('ti.sdo.fc.ires.hdvicp.HDVICP');

   HDVICP.debug = false;

   HDVICP.trace = true;

   var HDINTC = xdc.useModule('ti.sdo.fc.hdintc.HDINTC');

   HDINTC.interruptVectorId_0 = 10;

   HDINTC.interruptVectorId_1 = 11;

   HDINTC.hdvicpInterruptEventNo_0 = 29;

   HDINTC.hdvicpInterruptEventNo_1 = 39;

// HDINTC.biosInterruptVectorId_0 = 7;

   // HDINTC.biosInterruptVectorId_1 = 8;    

   // HDINTC.biosInterruptEventNo_0 = 30;    

   // HDINTC.biosInterruptEventNo_1 = 31;

请指正！EDMA3的资源量是从编码器的datasheet文件找出来的

Stanley Wang：

第1个问题，编解码必须在同一个线程里顺序执行，不能并行使用。即使放在两个线程中，也需要确保它们是在不同时间分别执行的。

如果编程中没有使用多线程，则崩溃可能是由于与codec不相关的其他的问题。需要了解进一步的细节。

第2个问题，是由于编解码算法需要占用多个EDMA资源，而EDMA的总数超过了系统限制。具体跟踪一下Codec Engine的调试信息吧。(设CE_DEBUG=1)

ipanda：

回复 Stanley Wang:

感谢Stanley Wang的回答

但是我想确认一下，是不是即使配置在不同的groupId里面，编解码都不能并行进行？在多线程并行的情况下，程序是能够正常跑起来的，只是长时间会导致资源冲突，dsp挂掉，如果单线程的话，dsp端的利用率会明显降低的，再次感谢！