我打算用28335的pwm触发ADC，不知道编的程序哪里出问题了，麻烦各位大神帮忙看看吧！！！

#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
// PWM start parameters
Uint16    *ExRamStart = (Uint16 *)0x100000;
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void Adcsample(void);
Uint32  EPwm1TimerIntCount;
Uint32  EPwm2TimerIntCount;
Uint32  EPwm3TimerIntCount;
Uint16  EPwm1_DB_Direction;
Uint16  EPwm2_DB_Direction;
Uint16  EPwm3_DB_Direction;

#define EPWM1_MAX_DB   0x03FF
#define EPWM2_MAX_DB   0x03FF
#define EPWM3_MAX_DB   0x03FF

#define EPWM1_MIN_DB   0
#define EPWM2_MIN_DB   0
#define EPWM3_MIN_DB   0

#define DB_UP   1
#define DB_DOWN 0

// ADC start parameters
#if (CPU_FRQ_150MHZ)     // Default – 150 ===========================================================================================================================MHz SYSCLKOUT
  #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
  #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
#endif
#define ADC_CKPS   0x0   // ADC module clock = HSPCLK/1      = 25.5MHz/(1)   = 25.0 MHz
#define ADC_SHCLK  0x1   // S/H width in ADC module periods                  = 2 ADC cycle
#define AVG        1000  // Average sample limit
#define ZOFFSET    0x00  // Average Zero offset
#define BUF_SIZE   512  // Sample buffer size

// Prototype statements for functions found within this file.
__interrupt void adc_isr(void);

// Global variables used in this example:
Uint16 LoopCount;
Uint16 ConversionCount;
Uint16 Voltage1[10];
Uint16 Voltage2[10];
void main(void)
{

 // Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
 int i;
 InitSysCtrl();

// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();  // Skipped for this example
    InitEPwm1Gpio();
    InitEPwm2Gpio();
    InitEPwm3Gpio();
  //zq
 
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
   DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
   InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
   IER = 0x0000;
   IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
   InitPieVectTable();

   EALLOW;  // This is needed to write to EALLOW protected register
   PieVectTable.ADCINT = &adc_isr;
   EDIS;    // This is needed to disable write to EALLOW protected registers

   InitAdc();         // For this example, init the ADC

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.

// StartCpuTimer0();
      EALLOW;
      SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
      EDIS;
      Adcsample();
      InitEPwm1Example();
      InitEPwm2Example();
      InitEPwm3Example();

      EALLOW;
            SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
            EDIS;
    EALLOW;
      SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
      EDIS;

      // Step 5. User specific code, enable interrupts
      // Initalize counters:
         EPwm1TimerIntCount = 0;
         EPwm2TimerIntCount = 0;
         EPwm3TimerIntCount = 0;

      // Enable CPU INT3 which is connected to EPWM1-3 INT:
         //IER |= M_INT3;

      // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
         //PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
         //PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
         //PieCtrlRegs.PIEIER3.bit.INTx3 = 1;

         // Enable ADCINT in PIE
            PieCtrlRegs.PIEIER1.bit.INTx6 = 1;

         IER |= M_INT1; // Enable CPU Interrupt 1

      // Enable global Interrupts and higher priority real-time debug events:
         EINT;   // Enable Global interrupt INTM
         ERTM;   // Enable Global realtime interrupt DBGM

         LoopCount = 0;
            ConversionCount = 0;

      // Step 6. IDLE loop. Just sit and loop forever (optional):
         for(;;)
         {
             asm("          NOP");
         for(i=1;i<=10;i++)
             {}
         }
}
                           //ADC模块
   void Adcsample()
   {

       // Specific ADC setup for this example:
          //AdcRegs.ADCTRL1.bit.ACQ_PS = 0xff;  // Sequential mode: Sample rate   = 1/[(2+ACQ_PS)*ADC clock in ns]
                               //                     = 1/(3*40ns) =8.3MHz (for 150 MHz SYSCLKOUT)
                //                     = 1/(3*80ns) =4.17MHz (for 100 MHz SYSCLKOUT)
                // If Simultaneous mode enabled: Sample rate = 1/[(3+ACQ_PS)*ADC clock in ns]
          AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
          //AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;        // 1  Cascaded mode
          AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA3 as 1st SEQ1 conv.
          AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x0; // Setup ADCINA2 as 2nd SEQ1 conv.
          //AdcRegs.ADCTRL1.bit.CONT_RUN = 1;       // Setup continuous run
          //AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1;       // Enable Sequencer override feature
          AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x1;  // convert and store in 8 results registers
          AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
          AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;  // Enable SEQ1 interrupt (every EOS)
   }

              //PWM模块

   void InitEPwm1Example()
   {

     EPwm1Regs.TBPRD =7500; // Period = 900 TBCLK counts
     EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
     EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
     EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
     EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
     EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
     EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
     EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

     EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
     EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
     EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
     EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
     EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A
     EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
     EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
     EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
     EPwm1Regs.DBFED = 200; // FED = 20 TBCLKs
     EPwm1Regs.DBRED = 200; // RED = 20 TBCLKs
     EPwm1Regs.CMPA.half.CMPA = 3750; // adjust duty for output EPWM1A

     EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
     EPwm1Regs.ETSEL.bit.SOCASEL = 4;       // Select SOC from from CPMA on upcount
     EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event
   }

   void InitEPwm2Example()
   {
     EPwm2Regs.TBPRD = 7500; // Period = 900 TBCLK counts
     EPwm2Regs.TBPHS.half.TBPHS = 5000; // Phase = 300/900 * 360 = 120 deg
     EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
     EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
     EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)
     EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
     EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
     EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
     EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

     EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
     EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
     EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
     EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
     EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A
     EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
     EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
     EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complementary
     EPwm2Regs.DBFED = 20; // FED = 20 TBCLKs
     EPwm2Regs.DBRED = 20; // RED = 20 TBCLKs
     EPwm2Regs.CMPA.half.CMPA = 3750; // adjust duty for output EPWM1A

   }

   void InitEPwm3Example()
   {

    EPwm3Regs.TBPRD = 7500; // Period = 900 TBCLK counts
     EPwm3Regs.TBPHS.half.TBPHS = 5000; // Phase = 300/900 * 360 = 120 deg
     EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
     EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
     EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; // Count UP on sync (=240 deg)
     EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
     EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
     EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
     EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

     EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
     EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
     EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
     EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
     EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM3Ai
     EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
     EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
     EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
     EPwm3Regs.DBFED = 20; // FED = 20 TBCLKs
     EPwm3Regs.DBRED = 20; // RED = 20 TBCLKs
     EPwm3Regs.CMPA.half.CMPA = 3750; // adjust duty for output EPWM1A

   }

__interrupt void  adc_isr(void)
   {
     Voltage1[ConversionCount] = AdcRegs.ADCRESULT0 >>4;
     Voltage2[ConversionCount] = AdcRegs.ADCRESULT1 >>4;

     // If 40 conversions have been logged, start over
     if(ConversionCount == 9)
     {
        ConversionCount = 0;
     }
     else
     {
         ConversionCount++;
     }

     // Reinitialize for next ADC sequence
     AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
     AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
     PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE

     return;
   }

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// No more.
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