TI中文支持网Hello,
I got a problem when using the vpif interface of DM6467.
When I read the user guide of vpif 
I think it means that when I configure this bit of CH0_CTRL register as 0, the input data should be changed at the rising edge of the input clock,and , in turn , the vpif interface will capture the data at the falling edge of th input clock. And the vice versa.
But the fact is just in the opposite side.
When I control the input data being changed at the rising edge of the input clock, and configure this bit of CH0_CTRL register as 0, sometimes the vpif interface cannot receive video data properly.
If I control the input data being changed at the rising edge of the input clock, and configure this bit of CH0_CTRL register as 1, the vpif interface will receive video data properly all the time.
So I wonder if there's something wrong with the vpif datasheet or if I have a misunderstanding of it.
Is there anybody can help me ? Thank you very much!
Chris Meng：
你好，
我认为这需要从输入，或者输出的角度来看。
如果是输入口，时钟上升沿有效，那就需要输出的数据在下降沿输出，这样做时钟的上升沿就可以正确采集到数据。
如果是输出口，时钟上升沿有效，据需要在上升沿发出数据，而接收端需要在时钟的下降沿接受数据。
whh1990：
回复 Chris Meng:
vpif 接口的channel0就是输入口。我现在不理解，配置与时钟的关系。我们都知道，如果数据在时钟上升沿变化，那么我们在下降沿采集才不会出错。比如，我们是通过FPGA向VPIF接口送数据的，配置成0时，FPGA端输入数据应该是在时钟上升沿变化还是下降沿变化？
