TI中文支持网项目需要用wince写GPMC驱动和FPGA双口ram通信。我是参考linux的GPMC和FPGA通信驱动编写。我在linu，示波器x下测试双口ram能正常工作。
代码如下，但是很多可能有错或理解不清，只能读写gpmc的寄存器，但是无法读写FPGA的ram数据，示波器也没信号
在bsp_padcfg.h中添加
#define FPGA_PADS \
PAD_ENTRY(GPMC_AD0, MODE(0) | AM335X_PIN_INPUT_PULLUP) \
PAD_ENTRY(GPMC_AD1, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD1 */ \
PAD_ENTRY(GPMC_AD2, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD2 */ \
PAD_ENTRY(GPMC_AD3, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD3 */ \
PAD_ENTRY(GPMC_AD4, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD4 */ \
PAD_ENTRY(GPMC_AD5, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD5 */ \
PAD_ENTRY(GPMC_AD6, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD6 */ \
PAD_ENTRY(GPMC_AD7, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD7 */ \
PAD_ENTRY(GPMC_AD8, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD8 */ \
PAD_ENTRY(GPMC_AD9, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD9 */ \
PAD_ENTRY(GPMC_AD10, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD10 */ \
PAD_ENTRY(GPMC_AD11, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD11 */ \
PAD_ENTRY(GPMC_AD12, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD12 */ \
PAD_ENTRY(GPMC_AD13, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD13 */ \
PAD_ENTRY(GPMC_AD14, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD14 */ \
PAD_ENTRY(GPMC_AD15, MODE(0) | AM335X_PIN_INPUT_PULLUP) /* NOR_AD15 */ \
PAD_ENTRY(GPMC_A0, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD0 */ \
PAD_ENTRY(GPMC_A1, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD1 */ \
PAD_ENTRY(GPMC_A2, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD2 */ \
PAD_ENTRY(GPMC_A3, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD3 */ \
PAD_ENTRY(GPMC_A4, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD4 */ \
PAD_ENTRY(GPMC_A5, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD5 */ \
PAD_ENTRY(GPMC_A6, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD6 */ \
PAD_ENTRY(GPMC_A7, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD7 */ \
PAD_ENTRY(GPMC_A8, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD8 */ \
PAD_ENTRY(GPMC_A9, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD9 */ \
PAD_ENTRY(GPMC_A10, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD10 */ \
PAD_ENTRY(GPMC_A11, MODE(0) | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA) /* NOR_AD11 */ \
PAD_ENTRY(GPMC_ADVN_ALE, MODE(0) | AM33XX_PULL_DISA) /* NAND_ADV_ALE */ \
PAD_ENTRY(GPMC_OEN_REN, MODE(0) | AM33XX_PULL_DISA) /* NAND_OE */ \
PAD_ENTRY(GPMC_WEN, MODE(0) | AM33XX_PULL_DISA) /* NAND_WEN */ \
PAD_ENTRY(GPMC_BE0N_CLE, MODE(0) | AM33XX_PULL_DISA) /* NAND_BE_CLE */ \
PAD_ENTRY(GPMC_CSN1, MODE(0) | AM33XX_PULL_DISA) /* MMC1_CLK */ \
PAD_ENTRY(GPMC_CLK, MODE(0) | AM33XX_PULL_DISA)
在bsp_padcfg.c中添加
{ FPGAPads, AM_DEVICE_FPGA, PROFILE_3, DEV_ON_DGHTR_BRD},
最后编写驱动fpga.c
#define STNOR_GPMC_CONFIG1 0x28601000 // no wait, 16 bit, non multiplexed
#define STNOR_GPMC_CONFIG2 0x00011001
#define STNOR_GPMC_CONFIG3 0x00020201 // we don't use ADV
#define STNOR_GPMC_CONFIG4 0x08031003
#define STNOR_GPMC_CONFIG5 0x000f1111
#define STNOR_GPMC_CONFIG6 0x0f030080
#define BSP_GPMC_PSOC_CONFIG7 0x00000F41 // Base address 0x1000000, 16MB window
#define BSP_GPMC_PSOC_CONFIG7_1 0x00000F01
DWORD FGA_Init(LPCTSTR szContext, LPCVOID pBusContext)
{
DWORD rc = (DWORD)NULL;
NKDbgPrintfW(TEXT("FPGA init.\n"));
PHYSICAL_ADDRESS pa;
InitializeCriticalSection(&g_csOpen);
InitializeCriticalSection(&g_csRead);
InitializeCriticalSection(&g_csWrite);
FpgaDevice *pDevice = NULL;
pDevice = (FpgaDevice *)LocalAlloc(LPTR, sizeof(FpgaDevice));
if (pDevice == NULL) {
NKDbgPrintfW(TEXT("FPGA init error.\n"));
return -1; }
int error;
UINT32 val;
UINT32 vison;
pa.QuadPart = GPMC_BASE_ADDR;
// AM3XX_GPMC_REGS_PA is defined as 0x50000000
pDevice->pGpmc = (AM3XX_GPMC_REGS *)MmMapIoSpace(pa, sizeof(AM3XX_GPMC_REGS), FALSE);
DEBUGMSG(ZONE_ERROR,(L"pGpmc_base= %x\n", pDevice->pGpmc));
vison=INREG32(&pDevice->pGpmc->GPMC_REVISION);
DEBUGMSG(ZONE_ERROR,(L"vison = %d.%d\n",(vison >> 4) & 0x0f, vison & 0x0f));
OUTREG32(&pDevice->pGpmc->GPMC_CONFIG, BSP_GPMC_PSOC_CONFIG7_1); // disabling the chip select
DEBUGMSG(ZONE_ERROR,(L"gpmc base = %x\n",pDevice->pGpmc));
OUTREG32(&pDevice->pGpmc->GPMC_CONFIG, (INREG32(&pDevice->pGpmc->GPMC_CONFIG))|0x00000002); //setting LIMITEDADDRESS to 1.
val =INREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG7);
DEBUGMSG(ZONE_ERROR,(L"GPMC_CS_CONFIG7 value default 0x%x\n", val));
OUTREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG1, STNOR_GPMC_CONFIG1);
OUTREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG2, STNOR_GPMC_CONFIG2);
OUTREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG3, STNOR_GPMC_CONFIG3);
OUTREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG4, STNOR_GPMC_CONFIG4);
OUTREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG5, STNOR_GPMC_CONFIG5);
OUTREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG6, STNOR_GPMC_CONFIG6);
OUTREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG7, BSP_GPMC_PSOC_CONFIG7);
val =INREG32(&pDevice->pGpmc->CS[1].GPMC_CONFIG7);
DEBUGMSG(ZONE_ERROR,(L"GPMC_CS_CONFIG7 value 0x%x\n", val));
pa.QuadPart = 0x1000000;
pDevice->fpga_base = (volatile FPGAREG16 *)MmMapIoSpace(pa, 2048, FALSE);
DEBUGMSG(ZONE_ERROR,(L"fpga_base= %x\n", pDevice->fpga_base));
rc = (DWORD)pDevice;
return rc;
DWORD FGA_Read(DWORD context, VOID *pBuffer, DWORD size)
{ int status = 0,i,tmp;
RETAILMSG(ZONE_ERROR,(L"read here"));
int len; // UCHAR* pData = (UCHAR*)pBuffer;
FpgaDevice *pDevice =(FpgaDevice *)context; //EnterCriticalSection(&g_csRead); // VALIDATE_ADDR_PORT(basead)
DEBUGMSG(ZONE_ERROR,(L"fpga base = %x\n",pDevice->fpga_base));
len=size; for(i=0;i<len;i=i+2)
{
tmp = INREG16(&pDevice->fpga_base+i);
pDevice->userbuff[i] = tmp&0xff; pDevice->userbuff[i+1] = (tmp>>8)&0xff;
}
// DEBUGMSG(ZONE_ERROR,(L"read = %x%x\n",pBuffer[0],pBuffer[1]));
memcpy(pBuffer,pDevice->userbuff,size);
// LeaveCriticalSection(&g_csRead);
return size;
}
我想知道应该如何写，找不到参考资料
Chris Meng：
你好，
AM相关芯片的问题，请到sitara论坛：http://www.deyisupport.com/question_answer/dsp_arm/sitara_arm/f/25.aspx。
