TI中文支持网各位老师:
我用DM3730的GPMC的CS1访问FPGA,没有上系统,仅仅是做个试验,配置如下:
//GPMC address
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A1),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A2),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A3),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A4),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A5),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A6),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A7),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A8),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A9),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_A10),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
//GPMC data
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D0),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D1),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D2),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D3),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D4),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D5),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D6),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D7),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D8),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D9),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D10),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D11),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D12),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D13),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D14),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_D15),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
//GPMC cs
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nCS0),(IDIS | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nCS1),(IDIS | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nCS4),(IDIS | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nCS5),(IDIS | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nCS6),(IDIS | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nCS7),(IDIS | PTU | EN | M0));//MCBSP2—CLKS
//GPMC (read/write)
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_CLK),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nADV_ALE),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nOE),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nWE),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nBE0_CLE),(IDIS | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_nWP),(IEN | PTD | DIS | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_WAIT0),(IEN | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_WAIT1),(IEN | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_WAIT2),(IEN | PTU | EN | M0));//MCBSP2—CLKS
RGE_VALE((OMAP34XX_CTRL_BASE+CONTROL_PADCONF_GPMC_WAIT3),(IEN | PTU | EN | M0));//MCBSP2—CLKS
__raw_writel(0x10, GPMC_SYSCONFIG); // smart idle0xf41
__raw_writel(0x0, GPMC_IRQENABLE); // isr's sources masked
// __raw_writel(tval, GPMC_TIMEOUT_CONTROL);// timeout disable
// global settings
__raw_writel(0x0, GPMC_IRQENABLE); //isr's sources masked
__raw_writel(0, GPMC_TIMEOUT_CONTROL); //timeout disable
config = __raw_readl(GPMC_CONFIG);
config &= (~0xf00);
__raw_writel(config, GPMC_CONFIG);//配置等待信号及读写信号的电平。
// (*(int*)0x6e000150) = 0x00001000;
// (*(int*)0x6e000154) = 0x001e1e01;
// (*(int*)0x6e000158) = 0x00080300;
// (*(int*)0x6e00015c) = 0x1c091c09;
// (*(int*)0x6e000160) = 0x04181f1f;
// (*(int*)0x6e000164) = 0x00000FcF;
// (*(int*)0x6e000168) = 0x00000f6c; //配置与DM900一样
RGE_VALE(GPMC_CONFIG1_i_cs1,FPGA_GPMC_CONFIG1); //GPMC时钟没有初使化0x00080300 十六位 且混合地址且没有分频
RGE_VALE(GPMC_CONFIG2_i_cs1,FPGA_GPMC_CONFIG2);//0x00000001
RGE_VALE(GPMC_CONFIG3_i_cs1,FPGA_GPMC_CONFIG3);//0x1c091c09
RGE_VALE(GPMC_CONFIG4_i_cs1,FPGA_GPMC_CONFIG4);//0x04181f1f
RGE_VALE(GPMC_CONFIG5_i_cs1,FPGA_GPMC_CONFIG5);//0x00000FcF
RGE_VALE(GPMC_CONFIG6_i_cs1,FPGA_GPMC_CONFIG6);//0x00000f6c
RGE_VALE(GPMC_CONFIG7_i_cs1,0xf60);//0x00000f6c
#define GPMC_CONFIG1_i_cs2 0x6e0000c0
#define GPMC_CONFIG2_i_cs2 0x6e0000c4
#define GPMC_CONFIG3_i_cs2 0x6e0000c8
#define GPMC_CONFIG4_i_cs2 0x6e0000cc
#define GPMC_CONFIG5_i_cs2 0x6e0000d0
#define GPMC_CONFIG6_i_cs2 0x6e0000d4
#define GPMC_CONFIG7_i_cs2 0x6e0000d8 //cs2
#define FPGA_GPMC_CONFIG1 0x00000200
#define FPGA_GPMC_CONFIG2 0x000a0a00 //CSRDACCESSTIME=10, CSWRACCESSTIME=10
#define FPGA_GPMC_CONFIG3 0x00020200 //ADVRDOFFTIME=2, ADVWROFFTIME=2
#define FPGA_GPMC_CONFIG4 0x08050805 //OEOFFTIME=8, WEOFFTIME=8, OEONTIME=5, WEONTIME=5
#define FPGA_GPMC_CONFIG5 0x00080b0b //RDCYCLETIME=11, WRCYCLETIME=11
#define FPGA_GPMC_CONFIG6 0x08000000 //WRACCESSTIME=8
但用 *( int *)(0x10000000)=0x5500; var=*( int *)(0x10000000); 这两句操作时,PC指针老跑飞,提示地址出错,不知道错在哪了,请指教,在线等待,谢谢!!!!!
JIM：
需要用IOREMAP吗?急啊!!!!
Feng Dong：
回复 JIM:
linux相应的地址都是要映射的.
hailin li：
你好。 直接访问片选区域地址，程序跑飞的问题 解决了吗？ 我也遇到类似问题，求解答。谢谢
