TI中文支持网I am designing with DM8127 IPNC . The DDR3 chip I used in my circuit board was MT41J128M16HA-125. But unfortunately this MT41J128M16HA-125 are now obsolete. So I found the recommented alternative chip in MICRON official site ,which is MT41K128M16JT-125. From the datasheet ,I know that the difference between they two is that MT41K128M is a low-leverl chip but it is compatible to 1.5v volt work.
First of all, I have succeeded in 1st stage boot and 2nd stage boot and the kenerl boot in my board when I used the MT41J128M16HA-125 as DDR3 chip.
Then I alternate the MT41J with MT41K, I found I can't enter into 1st stage boot now.
I am now used MT41K128M16JT-125 in 1.5v volt ,the VTT is 0.75 volt,since the datasheet says MT41K can be compatible to 1.5v volt work. Am I right?
What I have done is the followint:
1. use JTAG to connect to the Cortex A8 processor: sc
2. Loading and Executing GEL File" IPNC_A8_DDR3.gel"
3.Loading And Running A8 Binary “nandflash-writer.out”
4.Start the application from Run -> Resume
5. see the following path on the CCS console.
Choose your operation
Enter 1 —> To Flash an Image
Enter 2 —> To ERASE the whole NAND
Enter 3 —> To EXIT
Select '1' to flash the binary to NAND
6.Enter image file path
7.Enter offset (in hex):
8. Choose the ECC scheme from given options
Enter 1 —> BCH 8 bit
Enter 2 —> HAM
Enter 3 —> T0 EXIT
Please enter ECC scheme type :
I select 1 here.
9. the program begins and after it is finished the following text is print:
Application is successfully flashed
NAND boot preparation was successful!
After all above has been done ,I find the 1st stage boot can't work.
When I am working with MT41J128M16HA ,the 1st stage boot is succeeded smoothly.But I failed when I use MT41K128M16HA NOW. Why?
I begin to read the code of 1st boot stage in uboot files.But I find it 's a huge project for me,and I have no idea about how to debug with the ddr3 part.
I am looking forward to getting some advice from you and appreciate for your help !
Louis：
Hi,
As the IPNC_A8_DDR3.gel script is running properly, and the DDR init should be passed, so I suppose your DDR3 device is bring-up. Then please go through the DDR3 leveling part and update your binaries: http://processors.wiki.ti.com/index.php?title=TI814x-DDR3-Init-U-Boot&redirect=no
corvin wang：
回复 Louis:
Hi，Louis
Thanks for your advice and I have tried it .
I am confused about my ddr3 leveling outcome ：
Enter 0 for DDR Controller 0 & 1 for DDR Controller 1 0DDR START ADDR=0x80000000
Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window0xa5
Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window0x34
Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window0x13Enter the input file Name Ti814x_Ratio_valuesRD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE WR DATA RATIO MAXIMUM VALUE DIDN'T CONVERGE WR DATA RATIO MINIMUM VALUE DIDN'T CONVERGE ********************************************************* Byte level Slave Ratio Search Program Values ********************************************************* BYTE3 BYTE2 BYTE1 BYTE0*********************************************************Read DQS MAX 0 20000007 0 0Read DQS MIN 33 0 0 0Read DQS OPT 80000019 10000003 0 0*********************************************************Read DQS GATE MAX 0 0 0 0Read DQS GATE MIN 0 0 0 0Read DQS GATE OPT 0 0 0 0*********************************************************Write DQS MAX 0 14 0 0Write DQS MIN 0 0 0 0Write DQS OPT 0 a 0 0*********************************************************Write DATA MAX 0 0 0 0Write DATA MIN 0 0 0 0Write DATA OPT 0 0 0 0*********************************************************
===== END OF TEST =====
corvin wang：
回复 corvin wang:
I just tried it on my old board ，which the ddr3 chip is MT41J128M16HA, THE outcome is below and I think it was right
********************************************************* Byte level Slave Ratio Search Program Values ********************************************************* BYTE3 BYTE2 BYTE1 BYTE0*********************************************************Read DQS MAX 6e 6e 74 72Read DQS MIN 6 6 4 4Read DQS OPT 3a 3a 3c 3b*********************************************************Read DQS GATE MAX 150 14e 13e 139Read DQS GATE MIN 9 0 0 0Read DQS GATE OPT ac a7 9f 9c*********************************************************Write DQS MAX 86 94 7d 8bWrite DQS MIN 0 0 0 0Write DQS OPT 43 4a 3e 45*********************************************************Write DATA MAX ba b8 b8 baWrite DATA MIN 4c 4c 4c 4cWrite DATA OPT 83 82 82 83*********************************************************
corvin wang：
回复 corvin wang:
I can connect the a8,and I can load, can run the program .
The only thing I have changed is that the ddr3.
What should I do the following?
