TI中文支持网dm6467_h264fhdvenc_01_10_02_05_production移植到DSPBIOS，有问题：
1.程序始终运行在HDVICP_wait函数，没有进入HDVICP_done函数。
2.通过H264输出地址，outobj.bufs，发现，只生成了35个左右的字节。不知道问什么
Chris Meng：
你好，
什么叫移植到bios？你是否有使用codec engine？
jin xin：
回复 Chris Meng:
我没有调用CE，我用的架构seed公司那种，dm6467_h264fhdvenc_01_10_02_05_production这个代码是运行在裸机上的，不能运行在DSPBIOS上，所以我把代码放入到DSPBIOS中，目前我已经移植完毕，但是运行到RMAN_assignResources函数总是报错，IRES_ENORESOURCE (7)错误，我怀疑是EDMA分配问题，但是我不知道如果分配，RMAN.C中的H264DEC_DM6467_EDMA3_RM_GLOBALCONFIG结构体我已经修改，具体见附件，但是错误依然
jin xin：
回复 jin xin:
EDMA3_RM_GblConfigParams H264DEC_DM6467_EDMA3_RM_GLOBALCONFIG = { /** Total number of DMA Channels supported by the EDMA3 Controller */ /** Total number of DMA Channels supported by the EDMA3 Controller */ 64u, /** Total number of QDMA Channels supported by the EDMA3 Controller */ 8u, /** Total number of TCCs supported by the EDMA3 Controller */ 64u, /** Total number of PaRAM Sets supported by the EDMA3 Controller */ 512u, /** Total number of Event Queues in the EDMA3 Controller */ 4u, /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ 4u, /** Number of Regions on this EDMA3 controller */ 8u,
/** * \brief Channel mapping existence * A value of 0 (No channel mapping) implies that there is fixed association * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ 1u,
/** Existence of memory protection feature */ 0u,
/** Global Register Region of CC Registers */ (void *)0x01C00000u, /** Transfer Controller (TC) Registers */ { (void *)0x01C10000u, (void *)0x01C10400u, (void *)0x01C10800u, (void *)0x01C10C00u, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL }, /** Interrupt no. for Transfer Completion */ EDMA3_CC_XFER_COMPLETION_INT, /** Interrupt no. for CC Error */ EDMA3_CC_ERROR_INT, /** Interrupt no. for TCs Error */ { EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT, EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT, EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT, EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT },
/** * \brief EDMA3 TC priority setting * * User can program the priority of the Event Queues * at a system-wide level. This means that the user can set the * priority of an IO initiated by either of the TCs (Transfer Controllers) * relative to IO initiated by the other bus masters on the * device (ARM, DSP, USB, etc) */ { 0u, 1u, 2u, 3u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Threshold level of number of events * that can be queued up in the Event queues. EDMA3CC error register * (CCERR) will indicate whether or not at any instant of time the * number of events queued up in any of the event queues exceeds * or equals the threshold/watermark value that is set * in the queue watermark threshold register (QWMTHRA). */ { 16u, 16u, 16u, 16u, 0u, 0u, 0u, 0u },
/** * \brief To Configure the Default Burst Size (DBS) of TCs. * An optimally-sized command is defined by the transfer controller * default burst size (DBS). Different TCs can have different * DBS values. It is defined in Bytes. */ { 64u, 64u, 64u, 64u, 0u, 0u, 0u, 0u },
/** * \brief Mapping from each DMA channel to a Parameter RAM set, * if it exists, otherwise of no use. */ { EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP },
/** * \brief Mapping from each DMA channel to a TCC. This specific * TCC code will be returned when the transfer is completed * on the mapped channel. */ { EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 4u, 5u, 6u, 7u, 8u, 9u, 10u, 11u, 12u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 40u, 41u, 42u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 48u, 49u, 50u, 51u, 52u, 53u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, },
/** * \brief Mapping of DMA channels to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. */ { EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 }};
static EDMA3_RM_InstanceInitConfig H264DEC_DM6467_EDMA3_RM_INSTCONFIG = { /* Resources owned by Region 1 */ /* ownPaRAMSets */ {0x0u, 0x0u, 0x0u, 0x0u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
/* ownDmaChannels */ {0xFFF0FF0Fu, 0xFF3FFE0Fu},//{0xCF00E00Fu, 0xFF3FF800u},
/* ownQdmaChannels */ {0x0000007Fu},
/* ownTccs */ {0xFFF0FF0Fu, 0xFF3FFE0Fu},
/* Resources reserved by Region 1 */ /* resvdPaRAMSets */ {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},
/* resvdDmaChannels 0x30FF1FF0u*/ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
/* resvdQdmaChannels */ {0x0u},
/* resvdTccs */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1} };
