TI中文支持网你好：
我们现在在DM36X平台的IPNC3.1内核下测试SPI，发现在davinci_spi_master.c中配置
iowrite32(0 | (8 << 24) | (08 << 16), davinci_spi->base + SPIDELAY); 编译后，用示波器测量clk, cs信号线，发现 tC2TDELAY 和 tT2CDELAY 总是为0， 理论上应该如图1，图2的波形才对
图1
图2
请问是什么原因导致tC2TDELAY 和 tT2CDELAY 总是为0 ？
谢谢
Chris Meng：
Yin,
请问SPIDAT1.CSHOLD是否配置为0, SPIDAT1.WDEL是否配置为1？
yin yin1：
回复 Chris Meng:
你好：
CSHOLD = 0；
SPIFMTn. timer_disable = 0； //18 bit of SPI Data Format Registers
SPIDAT1.WDEL 这个参数我没有配置，有关系嘛？
谢谢
Chris Meng：
回复 yin yin1:
Yin，
有关系，请参考spi user guide里面下面的内容：
WDEL Enable the delay counter at the end of the current transaction. Note: The WDEL bit is supported in master mode only. In slave mode, this bit will be ignored.
0 No delay will be inserted. However, SPIx_SCS[1:0] pins will still be de-activated for at least for twoSPI peripheral clock cycles if CSHOLD = 0.Note: In SPI, the duration for which the SPIx_SCS[1:0] pins remaining de-activated will alsodepend upon time taken to supply a new data after completing the shifting operation. If the internalbuffer TXBUF is already full, then the SPIx_SCS[1:0] pins will be de-asserted for at least two SPIperipheral clock cycles (if WDEL = 0).
1 After a transaction, WDELAY of the corresponding data format will be loaded into the delaycounter. No transaction will be performed until the WDELAY counter overflows. The SPIx_SCSpins will be de-activated for at least (WDELAY + 2) SPI peripheral clock_Period duration.
yin yin1：
回复 Chris Meng:
OK, 你说的是对的 🙂
谢谢
