TI中文支持网从文档了解到有低功耗 这个设置 ，请问 应该如何设置呢？设置GIO0 吗 ？没有什么用啊 还是需要设置什么寄存器？
12.5.1 Deep Sleep Mode Deep sleep mode is a special power down mode in which all device clocks are stopped and the internal oscillators are powered down. Registers and software states are preserved and upon recovery, the program may continue from where it left off with minimal overhead involved. When enabled, driving GIO[0] low will initiate Deep Sleep and driving GIO[0] high will initiate wakeup from deep sleep. The deep sleep power-down process works as follows: • The ARM prepares for power down, typically after an external microcontroller notifies the ARM to prepare for power down via an interrupt or serial communication. • The ARM puts DDR2 in its to self-refresh state. The program in DDR2 is preserved while DDR2 is in its self-refresh state. In the case of mDDR, you may utilize partial array self refresh (PASR) for additional power savings. • To reduce the chip stand-by power, power-down all the analog blocks (PLL cores, DDR PHY DLL, DDR PHY, USB PHY and Video DAC). • The ARM sets SLEEPENABLE in register DEEPSLEEP in the system module. • The ARM informs the microcontroller that it has initiated deep sleep and begins polling SLEEPCOMPLETE in DEEPSLEEP. During the recovery process, the ARM will wake up and detect that SLEEPCOMPLETE has changed. • The microcontroller transitions GIO0 from high to low and then continues to hold GIO0 low (for a minimum of 500 ns) until it desires to exit Deep Sleep mode. The transition of GIO0 from high to low creates a clock pulse advancing the deep sleep state machine. After this transition, all clocks are stopped and then the internal oscillators are powered down. • At this point, the device is in deep sleep mode; power is reduced to a minimum. The deep sleep wakeup process is as follows: • To initiate the wakeup process, the microcontroller transitions GIO0 from low to high. This transition creates a clock pulse advancing the Deep Sleep state machine. After this transition, the oscillators are powered up and allowed to stabilize and then all clocks are restarted. • The ARM detects that SLEEPCOMPLETE has changed • The ARM clears SLEEPENABLE in register DEEPSLEEP • The ARM brings DDR2 out of self refresh. • At this point the ARM resumes normal operation. The ARM may branch to program code preserved in DDR2. Register states are preserved.
Chris Meng：
James,
硬件支持deep sleep模式，进入和退出流程如文档上描述的。但目前没有相关软件demo的支持。
james ZHANG3：
回复 Chris Meng:
请问具体应该怎么设置呢？有没有相关代码 或示例
