请教关于DM8148的HDVPSS子系统采集16bit YUV 4:2:2视频数据的配置问题？

设计使用FPGA+DM8148的视频采集处理方案，使用FPGA采集外部视频进行格式的转换，转换为内嵌同步信号（embedded syncs）的16bit YUV数据，数据输出到DM8148的视频采集的VIP0接口；请问

1）VIP0接口支持内嵌同步的16bit视频输入吗？

2）支持的话，要有哪些部分需要修改？

Ternence_Hsu：

john shi

1）VIP0接口支持内嵌同步的16bit视频输入吗？

2）支持的话，要有哪些部分需要修改？

可以支持的，你的fpga输出按bt1120协议输出就可以，采集配置capure link 为 VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC 和 VPS_CAPT_VIDEO_IF_MODE_16BIT

/*** \brief Video capture operation mode
*/
typedef enum
{VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC = 0,/**< Single Channel non multiplexed mode */VPS_CAPT_VIDEO_CAPTURE_MODE_MULTI_CH_LINE_MUX_EMBEDDED_SYNC,/**< Multi-channel line-multiplexed mode */VPS_CAPT_VIDEO_CAPTURE_MODE_MULTI_CH_PIXEL_MUX_EMBEDDED_SYNC,/**< Multi-channel pixel muxed */VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VBLK,/**< Single Channel non multiplexed discrete sync mode with HSYNC andVBLK as control signals. */VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC,/**< Single Channel non multiplexed discrete sync mode with HSYNC andVSYNC as control signals. */VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK,/**< Single Channel non multiplexed discrete sync mode with ACTVID andVBLK as control signals. */VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC,/**< Single Channel non multiplexed discrete sync mode with ACTVID andVBLK as control signals. */VPS_CAPT_VIDEO_CAPTURE_MODE_MULTI_CH_LINE_MUX_SPLIT_LINE_EMBEDDED_SYNC,/**< Multi-channel line-multiplexed mode - split line mode */VPS_CAPT_VIDEO_CAPTURE_MODE_MAX/**< Maximum modes */
} Vps_CaptVideoCaptureMode;/*** \brief Video interface mode*/
typedef enum
{VPS_CAPT_VIDEO_IF_MODE_8BIT = 0,/**< Embedded sync mode:8bit - BT656 standard*/VPS_CAPT_VIDEO_IF_MODE_16BIT,/**< Embedded sync mode:16bit - BT1120 standard*/VPS_CAPT_VIDEO_IF_MODE_24BIT,/**< Embedded sync mode:24bit */VPS_CAPT_VIDEO_IF_MODE_MAX/**< Maximum modes */
} Vps_CaptVideoIfMode;