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关于TMS320F28335编写中spwm的相位问题

2017-05-18 分类：C2000™ 32位实时 MCU 阅读(264)

在三相PWM整流器中，三相桥臂的A.B.C三相导通的PWM波形应该相差120°，但是，在设置epwm模块的时候，发现设置epwm2和3的相位装载值分别位120都和240°，但是出来的波形三相同相位，请问怎么回事？

void ePWMs_Init(EPWMS *p)
{
 //——————-
 //initialize ePWM2
 //——————- InitEPwm1Gpio();
 // set TBCLK设定计数器的最大值，当使用上升下降计数模式时，三角波的周期为PeriodMax*2*TBCLK
 EPwm1Regs.TBPRD = p->PeriodMax;                   // (the period is PeriodMax * 2 * TBCLK) EPwm1Regs.TBPHS.half.TBPHS = 0x0000;              // phase is 0          相位为0
 EPwm1Regs.TBCTR = 0x0000;                         // clear the counter   计数器清零
 // set the compare value初始化比较值
 // EPwm1Regs.CMPA.half.CMPA=6250;                  // 调试用
 EPwm1Regs.CMPA.half.CMPA = 2200;                  // set compare A   设定ePWM1模块通道A的比较值
 EPwm1Regs.CMPB = 2800;                            // set compare B   设定ePWM1模块通道B的比较值
 
 // set counter mode 设定计数器的计数模式
 EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // up and down counter增减计数模式
 EPwm1Regs.TBCTL.bit.PHSEN=TB_ENABLE;              // enable phase 使用相位矫正功能
 EPwm1Regs.TBPHS.half.TBPHS=0x0000;
 EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;       // 在CTR=0时，产生同步信号
 EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;                // 1/clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = 0;                   // TBCLK = SYSCLKOUT/(CLKDIV*HSPCLKDIV)设定TBCLK与SYSCLKOUT的关系
 // setup shadowing  映射寄存器功能设定
 EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;       // enable shadow CMPA  使能CPMA的映射寄存器
 EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;       // enable shadow CMPB  使能CPMB的映射寄存器
 EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;     // load on zero        当CTR=0时，经映射寄存器CPMA的值装载到当前寄存器
 EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;     //                  当CTR=0时，经映射寄存器CPMA的值装载到当前寄存器
 // set actions设定功能限定单元的动作
 EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;                // set PWM1A on event A, up count      上升沿计数时，当CTR=CMPA时，将ePWM1设定为高电平
 EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;              // clear PWM1A on event A, down count  下降沿计数时，当CTR=CMPA时，将ePWM1设定为高电平
 
 // 设定ePWM1B的动作限定，当使用DeadBand模块时，这两条语句可以省略
 EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;              // clear PWM1B on event B, up count
 EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;                // set PWM1B on event B, down count
 // Setup Deadband设定死区模块
 //EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;        // 禁止死区功能
 EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;    // both epwmA and epwmB are enbale  ePWMA和ePWMB都添加死区
 EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;         // A is A and B is inversed.       ePWMA不翻转,ePWMB翻转
 //EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;         // B is B and A is inversed.       ePWMB不翻转,ePWMA翻转
 EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;            // ePWMA is the source for both falling and rising delay   ePWMA作为上升沿与下降延时的参考脉冲信号
 EPwm1Regs.DBRED = DBTIME_FED;                     // Rising edge delay time          设定上升沿延时时间
 EPwm1Regs.DBFED = DBTIME_FED;                     // Falling edge delay time         设定下降沿延时时间
 // 配置EPWM1模块的周期中断功能
 EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;  // 选择计数器值=0为中断事件
 EPwm1Regs.ETSEL.bit.INTEN = 1;             // 使能相应的中断
 EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;        // 每次中断事件发生时都产生一次中断请求
 EPwm1Regs.ETCLR.bit.INT = 1;               // 清中断标志位        //——————-
//initialize ePWM2
//——————- InitEPwm2Gpio();
 // set TBCLK
 EPwm2Regs.TBPRD = p->PeriodMax;                   // (the period is PeriodMax * 2 * TBCLK) EPwm2Regs.TBPHS.half.TBPHS = 0x0000;              // phase is 0
 EPwm2Regs.TBCTR = 0x0000;                         // clear the counter
 // set the compare value
 //EPwm2Regs.CMPA.half.CMPA=6250;                  //调试用
 EPwm2Regs.CMPA.half.CMPA = 2200;                  // set compare A
 EPwm2Regs.CMPB = 2800;                            // set compare B
 // set counter mode
 EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // up and down counter
 EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;            // enable phase
 EPwm2Regs.TBPHS.half.TBPHS =0x0078;
 EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;        // 接收上个模块产生的同步信号
 EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;                // 1/clock ratio to SYSCLKOUT
 EPwm2Regs.TBCTL.bit.CLKDIV = 0;
 // setup shadowing
 EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;       // enable shadow CMPA
 EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;       // enable shadow CMPB
 EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;     // load on zero
 EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
 // set actions
 EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;                // set PWM1A on event A, up count
 EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;              // clear PWM1A on event B, down count
  EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;              // clear PWM1B on event B, up count
 EPwm2Regs.AQCTLB.bit.CBD = AQ_SET;                // set PWM1B on event B, down count
 // Setup Deadband
 EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
 EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
 EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
 //EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;         // B is B and A is inversed.       ePWMB不翻转,ePWMA翻转
 EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
 EPwm2Regs.DBRED = DBTIME_RED;
 EPwm2Regs.DBFED = DBTIME_FED;
//——————-
//initialize ePWM3
//——————- InitEPwm3Gpio();
 // set TBCLK
 EPwm3Regs.TBPRD = p->PeriodMax; EPwm3Regs.TBPHS.half.TBPHS = 0x0000;             // phase is 0
 EPwm3Regs.TBCTR = 0x0000;                        // clear the counter
 // set the compare value
 //EPwm3Regs.CMPA.half.CMPA=6250;                 // 调试用
 EPwm3Regs.CMPA.half.CMPA = 2200;                 // set compare A
 EPwm3Regs.CMPB=2800;                             // set compare B
 // set counter mode
 EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;   // up and down counter
 EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;           // disable phase
 EPwm3Regs.TBPHS.half.TBPHS=0x00f0;
 EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;       // 接收上个模块产生的同步信号
 EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;               // 1/clock ratio to SYSCLKOUT
 EPwm3Regs.TBCTL.bit.CLKDIV = 0;                  // TBCLK = SYSCLKOUT/128  0.853us
 // setup shadowing
 EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;      // enable shadow CMPA
 EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;      // enable shadow CMPB
 EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;    // load on zero
 EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
 // set actions
 EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;               // set PWM1A on event A, up count
 EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;             // clear PWM1A on event B, down count
  EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR;             // clear PWM1B on event B, up count
 EPwm3Regs.AQCTLB.bit.PRD = AQ_SET;               // set PWM1B on event B, down count
 // Setup Deadband
 EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
 EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
 EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
 //EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;        // B is B and A is inversed.       ePWMB不翻转,ePWMA翻转
 EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
 EPwm3Regs.DBRED = DBTIME_RED;
 EPwm3Regs.DBFED = DBTIME_FED;
}

Eric Ma：

如果三相之间要有相位差，应该是在TBPHS 寄存器加在0， 120， 240度的计数值，这样当同步信号来的时候，这两个计数器的起始值就有相位差了。

ERIC

在三相PWM整流器中，三相桥臂的A.B.C三相导通的PWM波形应该相差120°，但是，在设置epwm模块的时候，发现设置epwm2和3的相位装载值分别位120都和240°，但是出来的波形三相同相位，请问怎么回事？

void ePWMs_Init(EPWMS *p)
{
 //——————-
 //initialize ePWM2
 //——————- InitEPwm1Gpio();
 // set TBCLK设定计数器的最大值，当使用上升下降计数模式时，三角波的周期为PeriodMax*2*TBCLK
 EPwm1Regs.TBPRD = p->PeriodMax;                   // (the period is PeriodMax * 2 * TBCLK) EPwm1Regs.TBPHS.half.TBPHS = 0x0000;              // phase is 0          相位为0
 EPwm1Regs.TBCTR = 0x0000;                         // clear the counter   计数器清零
 // set the compare value初始化比较值
 // EPwm1Regs.CMPA.half.CMPA=6250;                  // 调试用
 EPwm1Regs.CMPA.half.CMPA = 2200;                  // set compare A   设定ePWM1模块通道A的比较值
 EPwm1Regs.CMPB = 2800;                            // set compare B   设定ePWM1模块通道B的比较值
 
 // set counter mode 设定计数器的计数模式
 EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // up and down counter增减计数模式
 EPwm1Regs.TBCTL.bit.PHSEN=TB_ENABLE;              // enable phase 使用相位矫正功能
 EPwm1Regs.TBPHS.half.TBPHS=0x0000;
 EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;       // 在CTR=0时，产生同步信号
 EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;                // 1/clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = 0;                   // TBCLK = SYSCLKOUT/(CLKDIV*HSPCLKDIV)设定TBCLK与SYSCLKOUT的关系
 // setup shadowing  映射寄存器功能设定
 EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;       // enable shadow CMPA  使能CPMA的映射寄存器
 EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;       // enable shadow CMPB  使能CPMB的映射寄存器
 EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;     // load on zero        当CTR=0时，经映射寄存器CPMA的值装载到当前寄存器
 EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;     //                  当CTR=0时，经映射寄存器CPMA的值装载到当前寄存器
 // set actions设定功能限定单元的动作
 EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;                // set PWM1A on event A, up count      上升沿计数时，当CTR=CMPA时，将ePWM1设定为高电平
 EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;              // clear PWM1A on event A, down count  下降沿计数时，当CTR=CMPA时，将ePWM1设定为高电平
 
 // 设定ePWM1B的动作限定，当使用DeadBand模块时，这两条语句可以省略
 EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;              // clear PWM1B on event B, up count
 EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;                // set PWM1B on event B, down count
 // Setup Deadband设定死区模块
 //EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;        // 禁止死区功能
 EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;    // both epwmA and epwmB are enbale  ePWMA和ePWMB都添加死区
 EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;         // A is A and B is inversed.       ePWMA不翻转,ePWMB翻转
 //EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;         // B is B and A is inversed.       ePWMB不翻转,ePWMA翻转
 EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;            // ePWMA is the source for both falling and rising delay   ePWMA作为上升沿与下降延时的参考脉冲信号
 EPwm1Regs.DBRED = DBTIME_FED;                     // Rising edge delay time          设定上升沿延时时间
 EPwm1Regs.DBFED = DBTIME_FED;                     // Falling edge delay time         设定下降沿延时时间
 // 配置EPWM1模块的周期中断功能
 EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;  // 选择计数器值=0为中断事件
 EPwm1Regs.ETSEL.bit.INTEN = 1;             // 使能相应的中断
 EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;        // 每次中断事件发生时都产生一次中断请求
 EPwm1Regs.ETCLR.bit.INT = 1;               // 清中断标志位        //——————-
//initialize ePWM2
//——————- InitEPwm2Gpio();
 // set TBCLK
 EPwm2Regs.TBPRD = p->PeriodMax;                   // (the period is PeriodMax * 2 * TBCLK) EPwm2Regs.TBPHS.half.TBPHS = 0x0000;              // phase is 0
 EPwm2Regs.TBCTR = 0x0000;                         // clear the counter
 // set the compare value
 //EPwm2Regs.CMPA.half.CMPA=6250;                  //调试用
 EPwm2Regs.CMPA.half.CMPA = 2200;                  // set compare A
 EPwm2Regs.CMPB = 2800;                            // set compare B
 // set counter mode
 EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // up and down counter
 EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;            // enable phase
 EPwm2Regs.TBPHS.half.TBPHS =0x0078;
 EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;        // 接收上个模块产生的同步信号
 EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;                // 1/clock ratio to SYSCLKOUT
 EPwm2Regs.TBCTL.bit.CLKDIV = 0;
 // setup shadowing
 EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;       // enable shadow CMPA
 EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;       // enable shadow CMPB
 EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;     // load on zero
 EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
 // set actions
 EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;                // set PWM1A on event A, up count
 EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;              // clear PWM1A on event B, down count
  EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;              // clear PWM1B on event B, up count
 EPwm2Regs.AQCTLB.bit.CBD = AQ_SET;                // set PWM1B on event B, down count
 // Setup Deadband
 EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
 EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
 EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
 //EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;         // B is B and A is inversed.       ePWMB不翻转,ePWMA翻转
 EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
 EPwm2Regs.DBRED = DBTIME_RED;
 EPwm2Regs.DBFED = DBTIME_FED;
//——————-
//initialize ePWM3
//——————- InitEPwm3Gpio();
 // set TBCLK
 EPwm3Regs.TBPRD = p->PeriodMax; EPwm3Regs.TBPHS.half.TBPHS = 0x0000;             // phase is 0
 EPwm3Regs.TBCTR = 0x0000;                        // clear the counter
 // set the compare value
 //EPwm3Regs.CMPA.half.CMPA=6250;                 // 调试用
 EPwm3Regs.CMPA.half.CMPA = 2200;                 // set compare A
 EPwm3Regs.CMPB=2800;                             // set compare B
 // set counter mode
 EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;   // up and down counter
 EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;           // disable phase
 EPwm3Regs.TBPHS.half.TBPHS=0x00f0;
 EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;       // 接收上个模块产生的同步信号
 EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;               // 1/clock ratio to SYSCLKOUT
 EPwm3Regs.TBCTL.bit.CLKDIV = 0;                  // TBCLK = SYSCLKOUT/128  0.853us
 // setup shadowing
 EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;      // enable shadow CMPA
 EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;      // enable shadow CMPB
 EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;    // load on zero
 EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
 // set actions
 EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;               // set PWM1A on event A, up count
 EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;             // clear PWM1A on event B, down count
  EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR;             // clear PWM1B on event B, up count
 EPwm3Regs.AQCTLB.bit.PRD = AQ_SET;               // set PWM1B on event B, down count
 // Setup Deadband
 EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
 EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
 EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
 //EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;        // B is B and A is inversed.       ePWMB不翻转,ePWMA翻转
 EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
 EPwm3Regs.DBRED = DBTIME_RED;
 EPwm3Regs.DBFED = DBTIME_FED;
}

leping yao：

回复 Eric Ma:

EPwm2Regs.TBPHS.half.TBPHS =0x0078;

EPwm3Regs.TBPHS.half.TBPHS =0x00f0;

我设置了2和3的相位寄存器是120°和240°的，但是波形还是不对，是因为没有采样的原因吗？我做的开环看三相PWM波形，不对啊。

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