TI中文支持网目前，公司做项目碰到一个问题，一直找不到原因：
在使用DMA将SDRAM数据传输到内部RAM中时，第一包数据能产生中断，第二包数据就产生不了中断，程序如下，各位看下问题出在哪里，我们的数据是用包来传输的，先将要传输的目的地址 源地址，长度放入BUFF中，如果BUFF中无数据，则直接运行DMA，如果BUFF中有数据，则继续放入BUFF中，然后在DMA中断时读BUFF来传输下一包数据
interrupt void SdRamdmaIsr(void)
{
dma1_flag&=~bit(dma1_packed_rd);
dma1_packed_rd++;
dma1_packed_rd &= 0xf;
if(dma1_packed_wr != dma1_packed_rd)
{
dmaset(hDmaSdram,&dma1_packed[dma1_packed_rd]);
}
else
{
dma1_busy = 0;
}
}
unsigned int sdram_cpy(unsigned long dst,unsigned long src,unsigned int size)
{
unsigned int return_val = dma1_packed_wr;
dma1_flag|=bit(dma1_packed_wr);
dma1_packed[dma1_packed_wr].dst = dst;
dma1_packed[dma1_packed_wr].src = src;
dma1_packed[dma1_packed_wr].size = size;
dma1_packed_wr++;
dma1_packed_wr&= 0xf;
CHIP_FSET(IER0,DMAC1,0);
if(dma1_busy == 0)
{
dma1_busy = 1;
dmaset(hDmaSdram,&dma1_packed[dma1_packed_rd]);
}
CHIP_FSET(IER0,DMAC1,1);
return return_val;
}
void Ramdma_init(void)
{
Uint16 ramEventId,sdramEventId;
DMA_Config *p_dmaRamConfig;
DMA_Config *p_dmaSdRamConfig;
dma0_packed_wr = 0;
dma0_packed_rd = 0;
dma1_packed_wr = 0;
dma1_packed_rd = 0;
dma0_flag = 0;
dma1_flag = 0;
dma0_busy = 0;
dma1_busy = 0;
p_dmaRamConfig = (DMA_Config *)&dmaRamConfig;
p_dmaSdRamConfig = (DMA_Config *)&dmaSdRamConfig;
hDmaRam = DMA_open(DMA_CHA0,DMA_OPEN_RESET);
hDmaSdram = DMA_open(DMA_CHA1,DMA_OPEN_RESET);
/* Get interrupt event associated with DMA receive and transmit */
ramEventId = DMA_getEventId(hDmaRam);
sdramEventId = DMA_getEventId(hDmaSdram);
/* Clear any pending interrupts for DMA channels */
IRQ_clear(ramEventId);
IRQ_clear(sdramEventId);
/* Enable DMA interrupt in IER register */
IRQ_enable(ramEventId);
IRQ_enable(sdramEventId);
/* Place DMA interrupt service addresses at associate vector */
IRQ_plug(ramEventId,&RamdmaIsr);
IRQ_plug(sdramEventId,&SdRamdmaIsr);
/* Write values from configuration structure to DMA control regs */
DMA_config(hDmaRam,p_dmaRamConfig);
DMA_config(hDmaSdram,p_dmaSdRamConfig);
/* Enable DMA */
}
void dmaset(DMA_Handle hDma,t_dma_packed *packed)
{
DMA_RSETH(hDma,DMACSSAU,(packed->src >> 15)&0xFFFFu);
DMA_RSETH(hDma,DMACSSAL,(packed->src << 1) &0xFFFFu);
DMA_RSETH(hDma,DMACDSAU,(packed->dst >> 15)&0xFFFFu);
DMA_RSETH(hDma,DMACDSAL,(packed->dst << 1) &0xFFFFu);
DMA_RSETH(hDma,DMACEN,packed->size);
DMA_RSETH(hDma,DMACFN,1);
DMA_FSETH(hDma,DMACCR,EN,1);
}
jian guo1：
const DMA_Config dmaSdRamConfig = { DMA_DMACSDP_RMK ( DMA_DMACSDP_DSTBEN_BURST4, DMA_DMACSDP_DSTPACK_ON, DMA_DMACSDP_DST_DARAMPORT0, DMA_DMACSDP_SRCBEN_BURST4, DMA_DMACSDP_DSTPACK_ON, DMA_DMACSDP_SRC_EMIF, DMA_DMACSDP_DATATYPE_16BIT ), /* DMACSDP */ DMA_DMACCR_RMK( DMA_DMACCR_DSTAMODE_POSTINC, DMA_DMACCR_DSTAMODE_POSTINC, DMA_DMACCR_ENDPROG_DEFAULT, DMA_DMACCR_WP_DEFAULT, DMA_DMACCR_REPEAT_DEFAULT, DMA_DMACCR_AUTOINIT_OFF, DMA_DMACCR_EN_STOP, DMA_DMACCR_PRIO_LOW, DMA_DMACCR_FS_DISABLE, DMA_DMACCR_SYNC_DEFAULT ), /* DMACCR */ DMA_DMACICR_RMK( DMA_DMACICR_AERRIE_ON, DMA_DMACICR_BLOCKIE_OFF, DMA_DMACICR_LASTIE_OFF, DMA_DMACICR_FRAMEIE_ON, DMA_DMACICR_FIRSTHALFIE_OFF, DMA_DMACICR_DROPIE_ON, DMA_DMACICR_TIMEOUTIE_OFF ), /* DMACICR */ 0, /* DMACSSAL */ 0, /* DMACSSAU */ 0, /* DMACDSAL */ 0, /* DMACDSAU */ 0, /* DMACEN */ 0, /* DMACFN */ 0, /* DMACSFI */ 0, /* DMACSEI */ 0, /* DMACDFI */ 0 /* DMACDEI */};
jian guo1：
记不得上传配置包了
const DMA_Config dmaSdRamConfig = { DMA_DMACSDP_RMK ( DMA_DMACSDP_DSTBEN_BURST4, DMA_DMACSDP_DSTPACK_ON, DMA_DMACSDP_DST_DARAMPORT0, DMA_DMACSDP_SRCBEN_BURST4, DMA_DMACSDP_DSTPACK_ON, DMA_DMACSDP_SRC_EMIF, DMA_DMACSDP_DATATYPE_16BIT ), /* DMACSDP */ DMA_DMACCR_RMK( DMA_DMACCR_DSTAMODE_POSTINC, DMA_DMACCR_DSTAMODE_POSTINC, DMA_DMACCR_ENDPROG_DEFAULT, DMA_DMACCR_WP_DEFAULT, DMA_DMACCR_REPEAT_DEFAULT, DMA_DMACCR_AUTOINIT_OFF, DMA_DMACCR_EN_STOP, DMA_DMACCR_PRIO_LOW, DMA_DMACCR_FS_DISABLE, DMA_DMACCR_SYNC_DEFAULT ), /* DMACCR */ DMA_DMACICR_RMK( DMA_DMACICR_AERRIE_ON, DMA_DMACICR_BLOCKIE_OFF, DMA_DMACICR_LASTIE_OFF, DMA_DMACICR_FRAMEIE_ON, DMA_DMACICR_FIRSTHALFIE_OFF, DMA_DMACICR_DROPIE_ON, DMA_DMACICR_TIMEOUTIE_OFF ), /* DMACICR */ 0, /* DMACSSAL */ 0, /* DMACSSAU */ 0, /* DMACDSAL */ 0, /* DMACDSAU */ 0, /* DMACEN */ 0, /* DMACFN */ 0, /* DMACSFI */ 0, /* DMACSEI */ 0, /* DMACDFI */ 0 /* DMACDEI */};
