TI中文支持网我写了个程序，想让DSP CE1脚拉低。
程序如下：
for(;;)
{
souraddr = (unsigned int *)0x403c00;*souraddr=0xff;
delay();
delay();
souraddr = (unsigned int *)0x403800;*souraddr=0;
delay();
delay();
}
可是CE1脚一直是高。是不是EMIF没配置好？如何配置？谢谢！
ccb bcc：
高手支招啊
Shine：
回复 ccb bcc:
请问你用的是哪款DSP? CE1接的是什么memory? EMIF寄存器是怎么配置的？
ccb bcc：
回复 Shine:
TMS320VC5509
CPLD
/*SDRAM的EMIF设置*/EMIF_Config emiffig = { 0x221, //EGCR : the MEMFREQ = 00,the clock for the memory is equal to cpu frequence // the WPE = 0 ,forbiden the writing posting when we debug the EMIF // the MEMCEN = 1,the memory clock is reflected on the CLKMEM pin // the NOHOLD = 1,HOLD requests are not recognized by the EMIF 0xFFFF, //EMI_RST: any write to this register resets the EMIF state machine 0x3FFF, //CE0_1: CE0 space control register 1 // MTYPE = 011,Synchronous DRAM(SDRAM),16-bit data bus width 0xFFFF, //CE0_2: CE0 space control register 2 0x00FF, //CE0_3: CE0 space control register 3 // TIMEOUT = 0xFF; 0x1FFF, //CE1_1: CE0 space control register 1 // Asynchronous, 16Bit 0xFFFF, //CE1_2: CE0 space control register 2 0x00FF, //CE1_3: CE0 space control register 3 0x1FFF, //CE2_1: CE0 space control register 1 // Asynchronous, 16Bit 0xFFFF, //CE2_2: CE0 space control register 2 0x00FF, //CE2_3: CE0 space control register 3 0x1FFF, //CE3_1: CE0 space control register 1 // Asynchronous, 16Bit 0xFFFF, //CE3_2: CE0 space control register 2 0x00FF, //CE3_3: CE0 space control register 3 0x2911, //SDC1: SDRAM control register 1 // TRC = 8 // SDSIZE = 0;SDWID = 0 // RFEN = 1 // TRCD = 2 // TRP = 2 0x0410, //SDPER : SDRAM period register // 7ns *4096 0x07FF, //SDINIT: SDRAM initialization register // any write to this register to init the all CE spaces, // do it after hardware reset or power up the C55x device 0x0131 //SDC2: SDRAM control register 2 // SDACC = 0; // TMRD = 01; // TRAS = 0101; // TACTV2ACTV = 0001; };
