warning #10247-D: creating output section "MYSEC" without a SECTIONS specification-TI中文支持网

使用的CCS版本Code Composer Studio 6.0.1; 使用的芯片F28M36

使用tirtos_c2000_2_00_01_23，xdctools_3_30_03_47_core

以下为cmd文件，我新建了一个空的c2000的RTOS工程，在默认cmd文件最后一行增加了MYSEC，在main文件我定义了#pragma DATA_SECTION(DMABuf1,"MYSEC");编译的时候总是报warning #10247-D: creating output section "MYSEC" without a SECTIONS specification

在m3核，我也建了同样的工程，也在cmd和main文件做了同样的操作，编译没有warning，在线求解，谢谢

* ======== F28M36P63C2.cmd ========
* Define the memory block start/length for the F28M36P63C2 C28
*/

MEMORY
{
PAGE 0: /* Program Memory */

    FLASH       : origin = 0x100000, length = 0x3FF80
    BEGIN       : origin = 0x13FFF0, length = 0x2
   PAGE 1 :   /* Data Memory */
      M01SARAM    : origin = 0x0,      length = 0x800     /* on-chip RAM block M0, M1 */
    PIEVECT     : origin = 0xD00,    length = 0x100
    L03SARAM    : origin = 0x8000,   length = 0x4000    /* on-chip RAM block L0-L3 */
    S07SHRAM    : origin = 0xC000,   length = 0x8000
    CTOMMSGRAM : origin = 0x3F800, length = 0x400
    MTOCMSGRAM : origin = 0x3FC00, length = 0x400
}

SECTIONS
{
    /* Allocate program areas: */
    .text       : > FLASH   PAGE = 0
    .cinit      : > FLASH   PAGE = 0
    .pinit      : > FLASH   PAGE = 0
    .binit      : > FLASH   PAGE = 0
    ramfuncs    : LOAD = FLASH      PAGE = 0,
                  RUN = L03SARAM   PAGE = 1,
                  LOAD_START(_RamfuncsLoadStart),
                  LOAD_SIZE(_RamfuncsLoadSize),
                  LOAD_END(_RamfuncsLoadEnd),
                  RUN_START(_RamfuncsRunStart)

    /* Initalized sections go in Flash */
    .econst     : > FLASH   PAGE = 0
    .switch     : > FLASH   PAGE = 0

    /* Allocate uninitalized data sections: */
    .stack      : > M01SARAM | L03SARAM PAGE = 1
    .ebss       : > M01SARAM | L03SARAM PAGE = 1
    .esysmem    : > L03SARAM | M01SARAM PAGE = 1
    .cio        : > L03SARAM | M01SARAM PAGE = 1
    .args       : > L03SARAM | M01SARAM PAGE = 1

.MYSEC :>L03SARAM PAGE = 1
}

以下为main文件开头部分

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/cfg/global.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/knl/Semaphore.h>

#include <ti/sysbios/family/c28/Hwi.h>
#include "F28M36x_Device.h"     // F28M36x Headerfile Include File
#include "F28M36x_GlobalPrototypes.h"         // Prototypes for global functions
                                              // within the .c files.
#include <string.h>

#pragma DATA_SECTION(DMABuf1,"MYSEC");

。。。。。

Lingling wang：

我把我的main函数全都贴出来给大家看看，我需要用DMA,本想在定义2个DMARAML2，DMARAML3定义DMA的源和目标数组，但总是报 without a SECTIONS specification的错误，于是我就把工程里其它文件都删了，新建了一个工程，用系统默认的cmd，在L03SARAM增加MYSEC，也报同样的错误，实在想不通了

* ======== main.c ======== */

#include <xdc/std.h>

#include <xdc/runtime/Error.h>#include <xdc/runtime/System.h>#include <xdc/cfg/global.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>#include <ti/sysbios/knl/Event.h>#include <ti/sysbios/knl/Semaphore.h>

#include <ti/sysbios/family/c28/Hwi.h>#include "F28M36x_Device.h" // F28M36x Headerfile Include File#include "F28M36x_GlobalPrototypes.h" // Prototypes for global functions // within the .c files.#include <string.h>

#pragma DATA_SECTION(DMABuf1,"MYSEC");//#pragma DATA_SECTION(DMABuf2,"MYSEC");

// Buffer size#define BUF_SIZE 10#define AD_BUF_LEN 10

// Prototype statements for functions found within this file.void local_DINTCH1_ISR(UArg arg);ti_sysbios_family_c28_Hwi_Struct dmach1hwi;

Uint16 ADC_Buf[8];Uint32 CH1_Buf[10];Uint32 CH3_Buf[10];Uint32 g_ulDataCH1;Uint32 g_ulDataCH2;Uint32 g_ulDataCH3;Uint32 g_ulDataCH4;Uint16 pCnt;Uint16 src_test[10];volatile Uint16 DMABuf1[10];volatile Uint16 DMABuf2[10];volatile Uint16 *DMADest;volatile Uint16 *DMASource;volatile Uint32 transfer_count;

//—————————————————————————// InitGpio://—————————————————————————// This function initializes the Gpio to a known (default) state.// For more details on configuring GPIO's as peripheral functions,// refer to the individual peripheral examples and/or GPIO setup example.void InitGpio(void){ EALLOW;

// Each GPIO pin can be: // a) a GPIO input/output // b) peripheral function 1 // c) peripheral function 2 // d) peripheral function 3 // By default, all are GPIO Inputs GpioG1CtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 GpioG1CtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 GpioG1CtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO44 GpioG1CtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO45-GPIO63 GpioG1CtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 GpioG1CtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 GpioG1CtrlRegs.GPDMUX1.all = 0x0000; // GPIO functionality GPIO96-GPIO111 GpioG1CtrlRegs.GPDMUX2.all = 0x0000; // GPIO functionality GPIO112-GPIO127 GpioG1CtrlRegs.GPEMUX1.all = 0x0000; // GPIO functionality GPIO128-GPIO135

GpioG2CtrlRegs.GPGMUX1.all = 0x0000; // GPIO functionality GPIO192-199 GpioG2CtrlRegs.AIOMUX1.all = 0x0000; // Dig.IO funct. applies to // AIO2,4,6,10,12,14 GpioG2CtrlRegs.AIOMUX2.all = 0x0000; // Dig.IO funct. applies to // AIO18,20,22,26,28,30

GpioG1CtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs GpioG1CtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs GpioG1CtrlRegs.GPCDIR.all = 0x0000; // GPIO64-GPIO95 are inputs GpioG1CtrlRegs.GPDDIR.all = 0x0000; // GPIO96-GPIO127 are inputs GpioG1CtrlRegs.GPEDIR.all = 0x0000; // GPIO128-GPIO159 are inputs GpioG2CtrlRegs.GPGDIR.all = 0x0000; // GPIO192-199 are inputs GpioG2CtrlRegs.AIODIR.all = 0x0000; // // // AIO2,4,6,19,12,14,18,20,22,26,28,30 // are digital inputs

// Each input can have different qualification // a) input synchronized to SYSCLKOUT // b) input qualified by a sampling window // c) input sent asynchronously (valid for peripheral inputs only) GpioG1CtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT GpioG1CtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT GpioG1CtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO44 Synch to SYSCLKOUT GpioG1CtrlRegs.GPBQSEL2.all = 0x0000; // GPIO45-GPIO63 Synch to SYSCLKOUT GpioG1CtrlRegs.GPCQSEL1.all = 0x0000; // GPIO64-GPIO79 Synch to SYSCLKOUT GpioG1CtrlRegs.GPCQSEL2.all = 0x0000; // GPIO80-GPIO95 Synch to SYSCLKOUT GpioG1CtrlRegs.GPDQSEL1.all = 0x0000; // GPIO96-GPIO111 Synch to SYSCLKOUT GpioG1CtrlRegs.GPDQSEL2.all = 0x0000; // GPIO112-GPIO127 Synch to SYSCLKOUT GpioG1CtrlRegs.GPEQSEL1.all = 0x0000; // GPIO128-GPIO135 Synch to SYSCLKOUT GpioG2CtrlRegs.GPGQSEL1.all = 0x0000; // GPIO192-GPIO199 Synch to SYSCLKOUT

// Enable internal pull-up for the selected pins

// Pull-up enable should be set in the// GPIO_O_PUR register in the M3 code.

EDIS;}

void init_sys(void){

// Step 1. Initialize System Control: // PLL, WatchDog, enable Peripheral Clocks // This example function is found in the F28M36x_SysCtrl.c file. InitSysCtrl();

// Copy time critical code and Flash setup code to RAM // This includes the following functions: InitFlash(); // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart // symbols are created by the linker. Refer to the device .cmd file.// memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

// Call Flash Initialization to setup flash waitstates // This function must reside in RAM// InitFlash();

// Initialize the PIE control registers to their default state. // The default state is all PIE interrupts disabled and flags // are cleared. // This function is found in the F28M36x_PieCtrl.c file. // InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags: /*IER = 0x0000; IFR = 0x0000;*/

// Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). // This will populate the entire table, even if the interrupt // is not used in this example. This is useful for debug purposes. // The shell ISR routines are found in F28M36x_DefaultIsr.c. // This function is found in F28M36x_PieVect.c. //InitPieVectTable();

// Enable global Interrupts and higher priority real-time debug events: EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM // Initialize GPIO: InitGpio();//set the GPIO to it's default state. /* Explicit posting of Event_Id_00 by calling Event_post() */

}

void ConfigEpwm1( void ){ // Assumes ePWM1 clock is already enabled in InitSysCtrl(); EALLOW; // Enable SOCA and SOCB EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group EPwm1Regs.ETSEL.bit.SOCASEL = 0x4; // Select SOC from CMPA/CMPC on up count EPwm1Regs.ETSEL.bit.SOCASELCMP = 0x1; // CMPC

EPwm1Regs.ETPS.bit.SOCAPRD = 3; // Generate SOCA pulse on every 3rd event

// Time-base registers EPwm1Regs.TBPRD = 14999; // Set EPWM timer period EPwm1Regs.TBPHS.all = 0; // Time-Base Phase Register EPwm1Regs.TBCTR = 0; // Time-Base Counter Register EPwm1Regs.TBCTL.bit.PRDLD = 1; // Set Immediate load EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count-up mode: used for asymmetric PWM

EPwm1Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading EPwm1Regs.TBCTL.bit.SYNCOSEL = 3;

// Set TBCLK frequency EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // TBCLK = SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = 0;

// Setup shadow register load on ZERO EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; EPwm1Regs.CMPCTL.bit.LOADAMODE = 0; // load on CTR=Zero

// Set Compare values EPwm1Regs.CMPC = 500; EDIS;}

void StartDMACH1(void){ EALLOW; DmaRegs.CH1.CONTROL.bit.RUN = 1; EDIS;}

/* * ======== taskFxn ======== */Uint16 j=0,state=0;Void taskFxn(UArg a0, UArg a1){ Int16 i; Hwi_Params hwiParams;

System_printf("enter taskFxn()\n");

init_sys();

pCnt = 0; g_ulDataCH1 = 0; g_ulDataCH2 = 0; g_ulDataCH3 = 0; g_ulDataCH4 = 0; for(i=7;i>=0;i–) // 清帧缓冲区 { ADC_Buf[i] = 0; } for(i = 0; i < 10; i++) { src_test[i] = i+1; }

for(i=AD_BUF_LEN-1;i>=0;i–)//清缓冲区 { CH1_Buf[i] = 0;

CH3_Buf[i] = 0;

}

EALLOW; Hwi_Params_init(&(hwiParams)); Hwi_construct(&dmach1hwi, 80, local_DINTCH1_ISR, &(hwiParams), NULL); EDIS;

// Initialize the DMA EALLOW; // Set up SOURCE address: DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)(&src_test);//(&McbspaRegs.DRR2.all); // Point to beginning of source buffer DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)(&src_test);//(&McbspaRegs.DRR2.all);

// Set up DESTINATION address: DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &ADC_Buf[0]; DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &ADC_Buf[0];

// Set up BURST registers: DmaRegs.CH1.BURST_SIZE.all = 0; //0 1 word per burst DmaRegs.CH1.SRC_BURST_STEP = 0; //0 Not used when bust size is 1 word DmaRegs.CH1.DST_BURST_STEP = 0; //0 Not used when burst size is 1 word

// Set up TRANSFER registers: DmaRegs.CH1.TRANSFER_SIZE = 5; // 1024 burst per transfer DmaRegs.CH1.SRC_TRANSFER_STEP =0;//0xFFFF; //0 Don't change source addres between burst DmaRegs.CH1.DST_TRANSFER_STEP = 1; // Destination address increment by 1 between burst // Set up WRAP registers: DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum – don't want source wrap DmaRegs.CH1.SRC_WRAP_STEP = 0; // Not used for wrap disabled DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum – don't want destination wrap DmaRegs.CH1.DST_WRAP_STEP = 0; // Not used for wrap disabled // Set up MODE Register: DmaRegs.CH1.MODE.bit.PERINTSEL = 18;//epwm //11;//timer0 // 15 McBSPA receive interrupt as channel trigger DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable channel triggered by peripheral interrupt DmaRegs.CH1.MODE.bit.ONESHOT = 0; // Disable one shot mode DmaRegs.CH1.MODE.bit.CONTINUOUS = 0; // Enable continous run mode DmaRegs.CH1.MODE.bit.OVRINTE = 0; // disable the overflow interrupt DmaRegs.CH1.MODE.bit.DATASIZE = 0; // 16-bit data size transfers,1-32bit DmaRegs.CH1.MODE.bit.CHINTMODE = 1;// 0; //0 Generate interrupt to CPU at beginning of transfer DmaRegs.CH1.MODE.bit.CHINTE = 1; // Channel Interrupt to CPU enable

// Clear any spurious flags: DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags //DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags

DmaRegs.CH1.CONTROL.bit.RUN = 1;

EDIS;

ConfigEpwm1();

// Step 5. Start the DMA transfer_count = 0;

}

/* * ======== main ======== */Int main(){ Task_Handle task; Error_Block eb;

System_printf("enter main()\n");

Error_init(&eb); task = Task_create(taskFxn, NULL, &eb); if (task == NULL) { System_printf("Task_create() failed!\n"); BIOS_exit(0); }

BIOS_start(); /* does not return */ return(0);}

void local_DINTCH1_ISR(UArg arg){ register Uint32 DataTemp; Uint16 i;

DataTemp = ADC_Buf[0]; DataTemp <<= 16; DataTemp |= ADC_Buf[1]; g_ulDataCH1 = DataTemp;

DataTemp = ADC_Buf[2]; DataTemp <<= 16; DataTemp |= ADC_Buf[3]; g_ulDataCH2 = DataTemp;

DataTemp = ADC_Buf[4]; DataTemp <<= 16; DataTemp |= ADC_Buf[5]; g_ulDataCH3 = DataTemp;

DataTemp = ADC_Buf[6]; DataTemp <<= 16; DataTemp |= ADC_Buf[7]; g_ulDataCH4 = DataTemp;

CH1_Buf[pCnt] = g_ulDataCH1; CH3_Buf[pCnt] = g_ulDataCH2;

for(i = 0; i < 10; i++) { src_test[i] = src_test[i]+1; }

if(pCnt<AD_BUF_LEN-1) { pCnt++; } else { pCnt = 0; }

transfer_count++; PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; StartDMACH1();

}

使用的CCS版本Code Composer Studio 6.0.1; 使用的芯片F28M36

使用tirtos_c2000_2_00_01_23，xdctools_3_30_03_47_core

在m3核，我也建了同样的工程，也在cmd和main文件做了同样的操作，编译没有warning，在线求解，谢谢

* ======== F28M36P63C2.cmd ========
* Define the memory block start/length for the F28M36P63C2 C28
*/

MEMORY
{
PAGE 0: /* Program Memory */

    /* Initalized sections go in Flash */
    .econst     : > FLASH   PAGE = 0
    .switch     : > FLASH   PAGE = 0

.MYSEC :>L03SARAM PAGE = 1
}

以下为main文件开头部分

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/cfg/global.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/knl/Semaphore.h>

#pragma DATA_SECTION(DMABuf1,"MYSEC");

。。。。。

Lingling wang：

回复 Lingling wang:

我知道问题在哪了，cmd文件里写的是.MYSEC,但#pragma DATA_SECTION(DMABuf1,"MYSEC");写的是MYSEC，少了一个.

真是大意啊，折腾了好久

使用的CCS版本Code Composer Studio 6.0.1; 使用的芯片F28M36

使用tirtos_c2000_2_00_01_23，xdctools_3_30_03_47_core

在m3核，我也建了同样的工程，也在cmd和main文件做了同样的操作，编译没有warning，在线求解，谢谢

* ======== F28M36P63C2.cmd ========
* Define the memory block start/length for the F28M36P63C2 C28
*/

MEMORY
{
PAGE 0: /* Program Memory */

    /* Initalized sections go in Flash */
    .econst     : > FLASH   PAGE = 0
    .switch     : > FLASH   PAGE = 0

.MYSEC :>L03SARAM PAGE = 1
}

以下为main文件开头部分

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/cfg/global.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/knl/Semaphore.h>

#pragma DATA_SECTION(DMABuf1,"MYSEC");

。。。。。

Seven Han：

回复 Lingling wang:

.MYSEC :> L03SARAM PAGE = 1

#pragma DATA_SECTION(DMABuf1,".MYSEC");

以为是编译器的原因呢，这个.在大写前太小啦，不容易发觉。

使用的CCS版本Code Composer Studio 6.0.1; 使用的芯片F28M36

使用tirtos_c2000_2_00_01_23，xdctools_3_30_03_47_core

在m3核，我也建了同样的工程，也在cmd和main文件做了同样的操作，编译没有warning，在线求解，谢谢

* ======== F28M36P63C2.cmd ========
* Define the memory block start/length for the F28M36P63C2 C28
*/

MEMORY
{
PAGE 0: /* Program Memory */

    /* Initalized sections go in Flash */
    .econst     : > FLASH   PAGE = 0
    .switch     : > FLASH   PAGE = 0

.MYSEC :>L03SARAM PAGE = 1
}

以下为main文件开头部分

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/cfg/global.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/knl/Semaphore.h>

#pragma DATA_SECTION(DMABuf1,"MYSEC");

。。。。。

Lingling wang：

回复 Seven Han:

继续问一个问题，我想把编码器EQEP的位置信息通过DMA搬到指定区域，定时产生中断，但是手册里写的DMA Block Diagram里的C28x PERIPHERALS不包括EQEP,ram空间也只能用L2/L3，我可以修改cmd文件把EQEP改到RAML3空间里吗？

F28M36x_Headers_BIOS.cmd里这样修改（红色部分）

MEMORY{ PAGE 0: /* Program Memory */

PAGE 1: /* Data Memory */

DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ CSM : origin = 0x000AE0, length = 0x000020 /* code security module registers */

ADC1_RESULT : origin = 0x000B00, length = 0x000020 /* ADC1 Results register */ ADC2_RESULT : origin = 0x000B40, length = 0x000020 /* ADC2 Results register */

CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers (CPU Timer1 & Timer2 reserved TI use)*/ CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers (CPU Timer1 & Timer2 reserved TI use)*/

PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */

DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ ASYSCTRLCONFIG : origin = 0x001700, length = 0x000080 /* Analog System Control Configuration Registers */ FLASH_REGS : origin = 0x004000, length = 0x000300 /* Flash Control registers */ FLASH_ECC : origin = 0x004300, length = 0x000040 /* Flash/OTP ECC Error Log registers */ M3PLL : origin = 0x004400, length = 0x000010 /* M3 Clock Configuration Registers */

EPI_REGS : origin = 0x004430, length = 0x000010 /* EPI Registers */ RAM_REGS : origin = 0x004900, length = 0x000080 /* RAM Control registers */ RAM_ERR_REGS : origin = 0x004A00, length = 0x000080 /* RAM ECC/PARITY/ACCESS Error Log Registers */

CM_MC_IPC : origin = 0x004E00, length = 0x000040 /* C28 Control to Master IPC registers */ MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */

EPWM1 : origin = 0x005100, length = 0x000080 /* EPWM1 + HRPWM registers */ EPWM2 : origin = 0x005180, length = 0x000080 /* EPWM2 + HRPWM registers */ EPWM3 : origin = 0x005200, length = 0x000080 /* EPWM3 + HRPWM registers */ EPWM4 : origin = 0x005280, length = 0x000080 /* EPWM4 + HRPWM registers */ EPWM5 : origin = 0x005300, length = 0x000080 /* EPWM5 + HRPWM registers */ EPWM6 : origin = 0x005380, length = 0x000080 /* EPWM6 + HRPWM registers */ EPWM7 : origin = 0x005400, length = 0x000080 /* EPWM7 + HRPWM registers */ EPWM8 : origin = 0x005480, length = 0x000080 /* EPWM8 + HRPWM registers */ EPWM9 : origin = 0x005500, length = 0x000080 /* EPWM9 registers (no HRPWM) */ EPWM10 : origin = 0x005580, length = 0x000080 /* EPWM10 registers (no HRPWM) */ EPWM11 : origin = 0x005600, length = 0x000080 /* EPWM11 registers (no HRPWM) */ EPWM12 : origin = 0x005680, length = 0x000080 /* EPWM12 registers (no HRPWM) */

ECAP1 : origin = 0x005A00, length = 0x000020 /* Enhanced Capture 1 registers */ ECAP2 : origin = 0x005A20, length = 0x000020 /* Enhanced Capture 2 registers */ ECAP3 : origin = 0x005A40, length = 0x000020 /* Enhanced Capture 3 registers */ ECAP4 : origin = 0x005A60, length = 0x000020 /* Enhanced Capture 4 registers */ ECAP5 : origin = 0x005A80, length = 0x000020 /* Enhanced Capture 5 registers */ ECAP6 : origin = 0x005AA0, length = 0x000020 /* Enhanced Capture 6 registers */

//EQEP1 : origin = 0x005B00, length = 0x000040 /* Enhanced QEP 1 registers */ //EQEP2 : origin = 0x005B40, length = 0x000040 /* Enhanced QEP 2 registers */ //EQEP3 : origin = 0x005B80, length = 0x000040 /* Enhanced QEP 3 registers */ EQEP1 : origin = 0x00B000, length = 0x000040 /* Enhanced QEP 1 registers */ EQEP2 : origin = 0x00B040, length = 0x000040 /* Enhanced QEP 2 registers */ EQEP3 : origin = 0x00B080, length = 0x000040 /* Enhanced QEP 3 registers */

。。。。。。。。

* ======== F28M36P63C2.cmd ======== * Define the memory block start/length for the F28M36P63C2 C28 */

MEMORY{PAGE 0: /* Program Memory */

FLASH : origin = 0x100000, length = 0x3FF80 BEGIN : origin = 0x13FFF0, length = 0x2 PAGE 1 : /* Data Memory */ M01SARAM : origin = 0x0, length = 0x800 /* on-chip RAM block M0, M1 */ PIEVECT : origin = 0xD00, length = 0x100 //L03SARAM : origin = 0x8000, length = 0x4000 /* on-chip RAM block L0-L3 */ RAML01 :origin = 0x8000, length = 0x2000 RAML2 :origin = 0xA000, length = 0x1000 RAML3 :origin = 0xB000, length = 0x1000 S07SHRAM : origin = 0xC000, length = 0x8000 CTOMMSGRAM : origin = 0x3F800, length = 0x400 MTOCMSGRAM : origin = 0x3FC00, length = 0x400}

使用的CCS版本Code Composer Studio 6.0.1; 使用的芯片F28M36

使用tirtos_c2000_2_00_01_23，xdctools_3_30_03_47_core

在m3核，我也建了同样的工程，也在cmd和main文件做了同样的操作，编译没有warning，在线求解，谢谢

* ======== F28M36P63C2.cmd ========
* Define the memory block start/length for the F28M36P63C2 C28
*/

MEMORY
{
PAGE 0: /* Program Memory */

    /* Initalized sections go in Flash */
    .econst     : > FLASH   PAGE = 0
    .switch     : > FLASH   PAGE = 0

.MYSEC :>L03SARAM PAGE = 1
}

以下为main文件开头部分

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/cfg/global.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/knl/Semaphore.h>

#pragma DATA_SECTION(DMABuf1,"MYSEC");

。。。。。

Lingling wang：

回复 Lingling wang:

我按照上面修改编译了一下，报了以下错我，求指点

<Linking>"F:/PUMP/MCU/linear/F28M36x/MCU_C28_TEST/../cmd/c28/F28M36x_Headers_BIOS.cmd", line 80: error #10264: EQEP1 memory range overlaps existing memory range RAML3"F:/PUMP/MCU/linear/F28M36x/MCU_C28_TEST/../cmd/c28/F28M36x_Headers_BIOS.cmd", line 81: error #10264: EQEP2 memory range overlaps existing memory range RAML3"F:/PUMP/MCU/linear/F28M36x/MCU_C28_TEST/../cmd/c28/F28M36x_Headers_BIOS.cmd", line 82: error #10264: EQEP3 memory range overlaps existing memory range RAML3

使用的CCS版本Code Composer Studio 6.0.1; 使用的芯片F28M36

使用tirtos_c2000_2_00_01_23，xdctools_3_30_03_47_core

在m3核，我也建了同样的工程，也在cmd和main文件做了同样的操作，编译没有warning，在线求解，谢谢

* ======== F28M36P63C2.cmd ========
* Define the memory block start/length for the F28M36P63C2 C28
*/

MEMORY
{
PAGE 0: /* Program Memory */

    /* Initalized sections go in Flash */
    .econst     : > FLASH   PAGE = 0
    .switch     : > FLASH   PAGE = 0

.MYSEC :>L03SARAM PAGE = 1
}

以下为main文件开头部分

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/cfg/global.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/knl/Semaphore.h>

#pragma DATA_SECTION(DMABuf1,"MYSEC");

。。。。。

Lingling wang：

回复 Lingling wang:

看了datasheet， EQEP的区间不能改

warning #10247-D: creating output section "MYSEC" without a SECTIONS specification

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