TI中文支持网本人在28377D上调试ADC模块，针对12bit模式的B口和D口的配置如下：
void InitADC(void)
{
unsigned int i;
EALLOW;
//part1:set ADCCLK divider to /4
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdcdRegs.ADCCTL2.bit.PRESCALE = 6;
//part2:12bit ADC mode.
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//part3:Set pulse positions to late about INTFlag after ADC converted.
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//part4:power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//part5:delay for > 1ms to allow ADC time to power up
for(i = 0; i < 1000; i++){
asm(" RPT#255 || NOP");
}
//B:B0/1/2/3->SPD
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert adcinb0
AdcbRegs.ADCSOC0CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIGSEL;
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert adcinb1
AdcbRegs.ADCSOC1CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIGSEL;
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert adcinb2
AdcbRegs.ADCSOC2CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIGSEL;
AdcbRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC3 will convert adcinb3
AdcbRegs.ADCSOC3CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = ADCTRIGSEL;
//D:D0/1/2/3/4->TQ
AdcdRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert adcind0
AdcdRegs.ADCSOC0CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIGSEL;
AdcdRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert adcind1
AdcdRegs.ADCSOC1CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIGSEL;
AdcdRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert adcind2
AdcdRegs.ADCSOC2CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcdRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIGSEL;
AdcdRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC3 will convert adcind3
AdcdRegs.ADCSOC3CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcdRegs.ADCSOC3CTL.bit.TRIGSEL = ADCTRIGSEL;
AdcdRegs.ADCSOC4CTL.bit.CHSEL = 4; //SOC4 will convert adcind4
AdcdRegs.ADCSOC4CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcdRegs.ADCSOC4CTL.bit.TRIGSEL = ADCTRIGSEL;
EDIS;
AdcbRegs.ADCSOCFRC1.all = 0xF; //SOC0/1/2/3
AdcdRegs.ADCSOCFRC1.all = 0x1F; //SOC0/1/2/3/4
for(i = 0; i < 3; i++){
asm(" RPT#600 || NOP");
}
while(AdcaRegs.ADCCTL1.bit.ADCBSY);
}
上面代码中ADCACQPS2=30;ADCTRIGSEL=0即软件启动AD采样与转换；另SYSCLK=200MHz,ADCCLK=50MHz；
在具体的测试中设置TIMER0中断中用软件语句触发B口和D口的12bit数据采样转换，但是，在实际的测试中需要设定定时器的比较值为1000才看到AD转换结果寄存器有更新，看似12bit模式下AD转换的时间比较长；不知道这是怎么回事？
附：之前本人实现了单纯16bit差分模式下A口上8路过采样，且TIMER0的时间2.5us（定时器比较值为500），数据都能够正常显示和刷新的.
Eric Ma：
上面代码中ADCACQPS2=30;ADCTRIGSEL=0即软件启动AD采样与转换；另SYSCLK=200MHz,ADCCLK=50MHz；
在具体的测试中设置TIMER0中断中用软件语句触发B口和D口的12bit数据采样转换，但是，在实际的测试中需要设定定时器的比较值为1000才看到AD转换结果寄存器有更新，看似12bit模式下AD转换的时间比较长；不知道这是怎么回事？
附：之前本人实现了单纯16bit差分模式下A口上8路过采样，且TIMER0的时间2.5us（定时器比较值为500），数据都能够正常显示和刷新的.
ERIC:
12位ADC的时候，采样窗ACQPS可以设置成14，改小一点。
另外，要看看你12位和16位的测试，代码是否是一致对比的，别增加其他的延时。
