DSP28335,使用30M有源晶振，XCLKOUT时钟输出不对？设置是SYSOUT/2，XCLKOUT等于XTIMCLK，应该输出是75M,但是输出3.75M-TI中文支持网

void InitPeripheralClocks(void)
{
EALLOW;

// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0001;
SysCtrlRegs.LOSPCP.all = 0x0002;

// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
// XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Enable XCLKOUT
XintfRegs.XINTCNF2.bit.CLKOFF = 0;

// Peripheral clock enables set for the selected peripherals.
// If you are not using a peripheral leave the clock off
// to save on power.
//
// Note: not all peripherals are available on all 2833x derivates.
// Refer to the datasheet for your particular device.
//
// This function is not written to be an example of efficient code.

SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC

// *IMPORTANT*
// The ADC_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.

ADC_cal();

SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM

SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2

SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2

SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock

EDIS;
}

void InitXintf(void)
{
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.

// For an example of an XINTF configuration used with the
// F28335 eZdsp, refer to the examples/run_from_xintf project.

// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.

// All Zones———————————发表
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 0;

// Zone 0————————————
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
/* XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous

// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
*/
// Zone 6————————————
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 1;
XintfRegs.XTIMING6.bit.XWRACTIVE =1;
XintfRegs.XTIMING6.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 2;
XintfRegs.XTIMING6.bit.XRDACTIVE = 2;
XintfRegs.XTIMING6.bit.XRDTRAIL = 2;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 1;
XintfRegs.XTIMING6.bit.READYMODE = 0; // sample asynchronous

// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;

// Zone 7————————————
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous

// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;

// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.

InitXintf16Gpio();
// InitXintf32Gpio();

asm(" RPT #7 || NOP");

}

Seven Han：

/ XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT // XTIMCLK = SYSCLKOUT/2 XintfRegs.XINTCNF2.bit.XTIMCLK = 1;

默认情况下XCLKOUT = SYSCLKOUT/4具体解释如下：

The XCLKOUT signal is directly derived from the system clock SYSCLKOUT as shown in Figure 21.XCLKOUT can be either equal to, one-half, or one-fourth of SYSCLKOUT. By default, at power-up,XCLKOUT = SYSCLKOUT/4 or XCLKOUT = OSCCLK/16 .