TI中文支持网1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
Igor An：每次重新写TBPRD会把相位也一起重新加载。所以对于pwm2，每次都是从相位处开始计数，也就是300-100=200向300计数，整个计数阶段没有cmp=100的点，所以就不会发出pwm。
改变pwm周期可以不用每个中断都写入，就可以解决这个问题。
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
user3900194：
回复 Igor An:
EPwm2Regs.TBPRD = 299; // Set timer periodEPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120EPwm2Regs.TBCTR = 0x0000; // Clear counterEPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3TEPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN// Setup TBCLKEPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count upEPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLEEPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUTEPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 250;//
1、此处改为250，也还是不发波，我仿真时确实看到了，TBCTR值超过周期值TBPRD了，但是不知道为啥？
2、我是想每个中断改变一次周期值，不在中断中更新周期值，还有其它办法？
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
user3900194：
回复 Igor An:
请问变频移相，ti有例子程序可参考吗？谢谢1
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
user3900194：
回复 Igor An:
更新周期值后，即使从200开始计数向299后为啥不从0开始重新计数，反而从计数器大于周期值时，继续向上计数呢？
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
Igor An：
回复 user3900194:
因为你设置了TBPH相角。如果都从0开始跑相角不就一样了嘛。
每个周期都改同时要保证交错相移的话必然会导致一定概率出现没有比较点的情况，只有让pwm时基跑一个周期，下一个完整周期才会有波形发出来。
你可以把count up改成count up down，试试，会有波形出来，但其实还是会有丢cmp点的问题，刚刚更改周期的那个周期有一相发波应该还是不对的
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
user3900194：
回复 Igor An:
谢谢您的耐心指教，在中断中只更新周期值时，pwm2计数器，为何计数到周期值时不清零，而是继续向上计数。我仿真时，pwm2计数器大部分是竟然大于周期值。不明白？
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
user3900194：
回复 Igor An:
能否再指教下，在中断中只更新周期值时，pwm2计数器，为何计数到周期值时不清零，而是继续向上计数。我仿真时，pwm2计数器大部分是竟然大于周期值。不明白？
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;
EPwm2Regs.TBPRD = 299; 不发波EPwm3Regs.TBPRD = 299;
EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
Igor An：
回复 user3900194:
计数超过周期，这是非常异常的情况，我这边没有碰到过类似的状况。从芯片角度将，是不会出现这种状况的，如果观察到这个现象，那么大概率还是软件配置和调用处理不大合适或错误导致的。
可以对比PRD寄存器一起来看，是否有其他位置也刷新了这个寄存器等类似的情况。
我觉得可以先把整个机制再理顺一下，因为当前的这种发波方式是会导致一相有问题，我想当把整个机制理顺之后，一些奇怪现象有可能就不会发生了。
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
user3900194：
回复 Igor An:
好的，我再仔细对一下配置。我仿真时确实是发现计数器值，超过周期值了。是增模式，应该是，在移相的情况下，PWM2计数器值等于相移的值，然后计数到周期值，然后再从0开始计数。
现在的情况感觉是计数器等于相移值后，计数到相移值+周期值后，再降到相移值，然后再计数到周期值，循环往复。
1、配置如下，以PWM1为基准，PMW2移相120，PWM3移相240
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example(); InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//PWM1初始化
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 299; // 200K
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //4T 同步顺流TB_SYNC_IN
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // 1t主模式
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// Active Low PWMs – Setup Deadband
/* EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;*/
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//pwm2初始化
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 299; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300-100; //2T Phase is 120
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1T 从模式TB_DISABLE
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// Setup compare EPwm2Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
//pwm3初始化
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 299; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 300-200; // Phase is 240
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// 3T
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //4T TB_CTR_ZERO TB_SYNC_IN
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //T Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
// Setup compare EPwm3Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm3Regs.AQCTLA.bit.ZRO= AQ_SET;//180412
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
// EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event}
以上初始化完毕后，在其它地方没有PWM做任何更改，然后主main程序for循环
正常情况1：pwm1/2/3能够正常发板，pwm2移相120，pwm3移相240
for(;;)
{
asm(" NOP");
}
异常情况2：在中断中，对TBPRD重新再次赋值一次，pwm1能够正常发板，pwm2不能发波，pwm3正常发波，移相240
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = 299;EPwm2Regs.TBPRD = 299; 不发波
EPwm3Regs.TBPRD = 299; EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
请问各位大侠，为什么在中断更新TBPRD一次后，PWM2就不能发波了，更别提移相了。但是pwm3正常。移相需要额外配置啥嘛？
user3900194：
回复 Igor An:
你好，我现在在中断中更新周期值和移相值，但是放到28035的cla中更新又不行了，又出现了PWM2的计数器值大于周期值了，EPwm1Regs.TBPRD =299; //EPwm2Regs.TBPRD =299; //EPwm3Regs.TBPRD =299; //EPwm2Regs.TBPHS.half.TBPHS = 299-100;EPwm3Regs.TBPHS.half.TBPHS = 299-200;
