DLP4500驱动板FLASH电路

请问，DLPLCR4500投影模块中图纸中，FLASH与DLP350控制器之间控制信号线之间有设计阻抗匹配电阻，为何数据线和地址线与DLP350之间无阻抗匹配电阻？该处是否对阻抗无要求？在布线时，对DLPC350至FLASH之间的走线长度是否有要求？

Kevin Shi：

您好！
请参考
www.ti.com/…/dlpc350.pdf
Page38
These timing values assume a maximum single direction trace length of 75 mm. When an additional flash is used
in conjunction with the boot flash, stub lengths must be kept short and located as close as possible to the flash
end of the route.
以及section11的layout guide
这是DLP4500 EVM的layout，可以作为参考
www.ti.com/…/tidc086