TI中文支持网各位，
看到RM42L432技术手册中的FLASH模块自带SECDED功能，是否可以理解成61508对invaviable memory的诊断措施modified checksum？？
另外，是否有可能按照标准对FLASH进行CRC校验，以达到更高的诊断覆盖率？
mirrored FLASH是否会起到对比的作用，看到它们都是TCM！FLASH在进行读操作的时候，mirrored flash是否已经起作用了？
gaoyang9992006：
同时采用汉明码和CRC校验应该是可行的。
SZ1：
Hi Geng,
ECC的诊断覆盖率更高。 当然ECC和Flash CRC在RM42L432上都可以实现。具体可以参考Safety Manual 上的说明：
7.39 Flash Contents Check by Hardware CRC
The platform includes a hardware cyclic redundancy check (CRC) implementing the ISO CRC-64 standard polynomial. The CRC module can be used to test the integrity of Flash contents by calculating a CRC for all Flash contents and comparing this value to a previously generated "golden" CRC. The read of Flash contents to the CRC can be done by CPU or the DMA. The comparison of results, indication of fault, and fault response are the responsibility of the software managing the test. It is highly recommended to perform a CRC integrity check of Flash contents at boot time. The cyclical check applied by the hardware CRC module provides an inherent level of self checking (auto-coverage), which can be considered for application in latent fault diagnostics.
7.40 Flash ECC
The on-chip Flash memory is supported by single error correction, dual error detection (SECDED) errorcorrecting code (ECC) diagnostic. It is connected by a 64-bit-wide data bus interface (ATCM) to the Cortex-R4F CPU. In this SECDED scheme, an 8-bit code word is used to store the ECC data as calculated over the 64-bit data bus. The ECC logic for the ATCM Flash access is located in the Cortex-R4F CPU. All ATCM transactions have ECC on the data payload. ECC evaluation is done by the ECC control logic inside the CPU. This scheme provides end-to-end diagnostics on the transmissions between the CPU and Flash memory. Detected uncorrectable errors result in a processor abort or bus error depending on the requesting master. Detected correctable errors can be corrected or not corrected, depending on whether correction functionality is enabled. The address of the memory, which includes the ECC error, is logged in the CPU. For more details, see the Cortex-R4 and Cortex-R4F Technical Reference Manual located at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363e/index.html. It is possible to export error detection events from the CPU to the Flash wrapper, and then from the Flash wrapper to the ESM. This functionality is not enabled by default and must be configured by the software. The Cortex-R4F PMU must first be set to export events to an external monitor. Then the Flash wrapper must be configured to export the correctable and uncorrectable events to the ESM. The ECC logic for the Flash is disabled at reset and must be configured in both the CPU and the Flash wrapper. The diagnostic has separate controls for checking, correction, and read and modify and write functionality in the system control coprocessor that must be enabled via software. As the ECC diagnostic is implemented inside the CPU, its behavior is continuously checked via the lockstep functionality and can also be tested via the LBIST STC. The cyclical check applied by the ECC module provides an inherent level of self checking (auto-coverage), which can be considered for application in latent fault diagnostics.
具体的实现可以调用SafeTI Diagnostic Library 的API函数来比较方便的实现：
谢谢！
