RM57L843 spi与HET初始化冲突问题-TI中文支持网

背景交代：本人目前在调试的是RM57L843芯片，版本为B版。根据HAL Code Generator配置了SPI接口（SPI1、SPI3、SPI5），调试通过。后有配置了HET模块用于PWM输出，pwm0~PWM7均可输出。后来应用HET_IDE工具配置成13路PWM输出，也可测到所有输出。还配置了ADC1、EMIF、sci1~sci4、CAN1~CAN4、RTI(仅用于定时)。

问题描述：在综合测试时，main函数中完成以下工作：

int main(void)

{

rtiInit();

esmInit();

emif_ASYNC2Init();

gioInit();

sciInit();

adcInit();

canInit();

spiInit();

hetIint();

…………

}

后来测试显示，

情况1：使用HET_IDE生成的HET模块；如果执行了hetInit();则我的SPI的CLK测不到信号，SPI不正常工作（3组SPI）；如果不执行hetInit(),则SPI正常工作。

情况2：使用HET_IDE生成的HET模块；先执行spiInit();不执行hetInit(); 在执行SPI相关程序，SPI功能正常。SPI功能正常后再执行hetInit()后，在进行SPI相关程序，则SPI功能不正常。

情况3：使用HAL Code Generator配置HET模块。同情况1、2。

后来定位到hetInit()中的（VOID）memcpy((void *)hetRAM1,(const void*)het1PROGRAM,sizeof(het1PROGRAM));

如果屏蔽掉该语句，则SPI功能正常，但PWM无输出，该语句只是把数组放置到制定RAM中，为何会影响spi的clk.

关于时钟初始化：spi的clk用的是VCLK,het用的是VCLK2,在系统初始化时CCDIS写入的是0X20 除去VCLK2A 未使用，其他均打开了。

请教大神如何解决，或者有没有类似的情况啊

Susan Yang：

根据您的描述结合数据手册，SPI和N2HET是引脚复用的，个人感觉应该是您的配置有些问题

请问能否请您给出相关寄存器的配置以及使用的引脚情况？谢谢

lechi zhang：

回复 Susan Yang:

您好，感谢您的回复，我刚才又查了一下我的配置。我配置了SPI1 SPI3 SPI5 HET1

其中SPI1\SPI3\SPI5\HET1的引脚配置为：

SPI1
F18
MIBSPI1CLK

F19
MIBSPI1SIMO[0]

G18
MIBSPI1SOM1[0]

R2
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD/ECAP6

SPI3
V9
MIBSPI3CLK/AD1EXT_SEL/EQEP1A

V8
MIBSPI3SOMI/AD1EXT_ENA/ECAP2

V10
MIBSPI3NCS[0]/AD2EVT/EQEP1

SPI5
H19
MIBSPI5CLK/DMM_DATA[4/MII_TXEN/RMII_TXEN

J19
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]

J18
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]

E19
MIBSPI5NCS[0]/DMM_DATA[5]/EPWM4A

HET1
V2
N2HET1[1]/MIBSPI4NENA/N2HET2[8]/EQEP2A

W5
N2HET1[2]/MIBSPI4SIMO/EPWM3A

U1
N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/EQEP2B

B12
N2HET1[4]/MIBSPI4NCS[1]/EPWM4B

V6
N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/EPWM3B

T1
N2HET1[7]/MIBSPI4NCS[2]/N2HET[14]/EPWM7B

E18
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]

V7
N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/EPWM7A

F19
N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/NTZ1_3

E3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO

B4
N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV

A11
N2HET1[14]

N1
N2HET1[15]//MIBSPI1NCS[4]/N2HET2[22]/ECAP1

用配置工具也分别配置了各引脚，未发现有冲突的引脚

lechi zhang：

回复 Susan Yang:

您好，补充配置如下：

SPI配置如下：

void spiInit(void){/* USER CODE BEGIN (2) *//* USER CODE END */

/** @b initialize @b SPI1 */

/** bring SPI out of reset */ spiREG1->GCR0 = 0U; spiREG1->GCR0 = 1U;

/** SPI1 master mode and clock configuration */ spiREG1->GCR1 = (spiREG1->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ | 1U); /* MASTER */

/** SPI1 enable pin configuration */ spiREG1->INT0 = (spiREG1->INT0 & 0xFEFFFFFFU)| (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */

/** – Delays */ spiREG1->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ | (uint32)((uint32)0U << 16U) /* T2CDELAY */ | (uint32)((uint32)0U << 8U) /* T2EDELAY */ | (uint32)((uint32)0U << 0U); /* C2EDELAY */

/** – Data Format 0 */ spiREG1->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)74U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – Data Format 1 */ spiREG1->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)14U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – Data Format 2 */ spiREG1->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)14U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – Data Format 3 */ spiREG1->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)14U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – set interrupt levels */ spiREG1->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ | (uint32)((uint32)0U << 6U) /* OVRNINT */ | (uint32)((uint32)0U << 4U) /* BITERR */ | (uint32)((uint32)0U << 3U) /* DESYNC */ | (uint32)((uint32)0U << 2U) /* PARERR */ | (uint32)((uint32)0U << 1U) /* TIMEOUT */ | (uint32)((uint32)0U << 0U); /* DLENERR */

/** – clear any pending interrupts */ spiREG1->FLG |= 0xFFFFU;

/** – enable interrupts */ spiREG1->INT0 = (spiREG1->INT0 & 0xFFFF0000U) | (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ | (uint32)((uint32)0U << 6U) /* OVRNINT */ | (uint32)((uint32)0U << 4U) /* BITERR */ | (uint32)((uint32)0U << 3U) /* DESYNC */ | (uint32)((uint32)0U << 2U) /* PARERR */ | (uint32)((uint32)0U << 1U) /* TIMEOUT */ | (uint32)((uint32)0U << 0U); /* DLENERR */

/** @b initialize @b SPI1 @b Port */

/** – SPI1 Port output values */ spiREG1->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 25U); /* SOMI[1] */

/** – SPI1 Port direction */ spiREG1->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 25U); /* SOMI[1] */

/** – SPI1 Port open drain enable */ spiREG1->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 25U); /* SOMI[1] */

/** – SPI1 Port pullup / pulldown selection */ spiREG1->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 25U); /* SOMI[1] */

/** – SPI1 Port pullup / pulldown enable*/ spiREG1->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 25U); /* SOMI[1] */

/* SPI1 set all pins to functional */ spiREG1->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 25U); /* SOMI[1] */

/** – Initialize TX and RX data buffer Status */ g_spiPacket_t[0U].tx_data_status = SPI_READY; g_spiPacket_t[0U].rx_data_status = SPI_READY;

/** – Finally start SPI1 */ spiREG1->GCR1 = (spiREG1->GCR1 & 0xFEFFFFFFU) | 0x01000000U;

/** @b initialize @b SPI3 */

/** bring SPI out of reset */ spiREG3->GCR0 = 0U; spiREG3->GCR0 = 1U;

/** SPI3 master mode and clock configuration */ spiREG3->GCR1 = (spiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ | 1U); /* MASTER */

/** SPI3 enable pin configuration */ spiREG3->INT0 = (spiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */

/** – Delays */ spiREG3->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ | (uint32)((uint32)00U << 16U) /* T2CDELAY */ | (uint32)((uint32)0U << 8U) /* T2EDELAY */ | (uint32)((uint32)0U << 0U); /* C2EDELAY */

/** – Data Format 0 */ spiREG3->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)74U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – Data Format 1 */ spiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ | (uint32)((uint32)74U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */

/** – Data Format 2 */ spiREG3->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ | (uint32)((uint32)74U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */

/** – Data Format 3 */ spiREG3->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ | (uint32)((uint32)74U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */

/** – set interrupt levels */ spiREG3->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ | (uint32)((uint32)0U << 6U) /* OVRNINT */ | (uint32)((uint32)0U << 4U) /* BITERR */ | (uint32)((uint32)0U << 3U) /* DESYNC */ | (uint32)((uint32)0U << 2U) /* PARERR */ | (uint32)((uint32)0U << 1U) /* TIMEOUT */ | (uint32)((uint32)0U << 0U); /* DLENERR */

/** – clear any pending interrupts */ spiREG3->FLG |= 0xFFFFU;

/** – enable interrupts */ spiREG3->INT0 = (spiREG3->INT0 & 0xFFFF0000U) | (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ | (uint32)((uint32)0U << 6U) /* OVRNINT */ | (uint32)((uint32)0U << 4U) /* BITERR */ | (uint32)((uint32)0U << 3U) /* DESYNC */ | (uint32)((uint32)0U << 2U) /* PARERR */ | (uint32)((uint32)0U << 1U) /* TIMEOUT */ | (uint32)((uint32)0U << 0U); /* DLENERR */

/** @b initialize @b SPI3 @b Port */

/** – SPI3 Port output values */ spiREG3->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO */ | (uint32)((uint32)0U << 11U); /* SOMI */

/** – SPI3 Port direction */ spiREG3->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO */ | (uint32)((uint32)0U << 11U); /* SOMI */

/** – SPI3 Port open drain enable */ spiREG3->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO */ | (uint32)((uint32)0U << 11U); /* SOMI */

/** – SPI3 Port pullup / pulldown selection */ spiREG3->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO */ | (uint32)((uint32)1U << 11U); /* SOMI */

/** – SPI3 Port pullup / pulldown enable*/ spiREG3->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO */ | (uint32)((uint32)0U << 11U); /* SOMI */

/* SPI3 set all pins to functional */ spiREG3->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO */ | (uint32)((uint32)1U << 11U); /* SOMI */

/** – Initialize TX and RX data buffer Status */ g_spiPacket_t[2U].tx_data_status = SPI_READY; g_spiPacket_t[2U].rx_data_status = SPI_READY;

/** – Finally start SPI3 */ spiREG3->GCR1 = (spiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U;

/** @b initialize @b SPI5 */

/** bring SPI out of reset */ spiREG5->GCR0 = 0U; spiREG5->GCR0 = 1U;

/** SPI5 master mode and clock configuration */ spiREG5->GCR1 = (spiREG5->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ | 1U); /* MASTER */

/** SPI5 enable pin configuration */ spiREG5->INT0 = (spiREG5->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */

/** – Delays */ spiREG5->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ | (uint32)((uint32)0U << 16U) /* T2CDELAY */ | (uint32)((uint32)0U << 8U) /* T2EDELAY */ | (uint32)((uint32)0U << 0U); /* C2EDELAY */

/** – Data Format 0 */ spiREG5->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ | (uint32)((uint32)14U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – Data Format 1 */ spiREG5->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)14U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – Data Format 2 */ spiREG5->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)14U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – Data Format 3 */ spiREG5->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)1U << 16U) /* clock phase */ | (uint32)((uint32)14U << 8U) /* baudrate prescale */ | (uint32)((uint32)8U << 0U); /* data word length */

/** – set interrupt levels */ spiREG5->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ | (uint32)((uint32)0U << 6U) /* OVRNINT */ | (uint32)((uint32)0U << 4U) /* BITERR */ | (uint32)((uint32)0U << 3U) /* DESYNC */ | (uint32)((uint32)0U << 2U) /* PARERR */ | (uint32)((uint32)0U << 1U) /* TIMEOUT */ | (uint32)((uint32)0U << 0U); /* DLENERR */

/** – clear any pending interrupts */ spiREG5->FLG |= 0xFFFFU;

/** – enable interrupts */ spiREG5->INT0 = (spiREG5->INT0 & 0xFFFF0000U) | (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ | (uint32)((uint32)0U << 6U) /* OVRNINT */ | (uint32)((uint32)0U << 4U) /* BITERR */ | (uint32)((uint32)0U << 3U) /* DESYNC */ | (uint32)((uint32)0U << 2U) /* PARERR */ | (uint32)((uint32)0U << 1U) /* TIMEOUT */ | (uint32)((uint32)0U << 0U); /* DLENERR */

/** @b initialize @b SPI5 @b Port */

/** – SPI5 Port output values */ spiREG5->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 18U) /* SIMO[2] */ | (uint32)((uint32)0U << 19U) /* SIMO[3] */ | (uint32)((uint32)0U << 25U) /* SOMI[1] */ | (uint32)((uint32)0U << 26U) /* SOMI[2] */ | (uint32)((uint32)0U << 27U); /* SOMI[3] */

/** – SPI5 Port direction */ spiREG5->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 18U) /* SIMO[2] */ | (uint32)((uint32)0U << 19U) /* SIMO[3] */ | (uint32)((uint32)0U << 25U) /* SOMI[1] */ | (uint32)((uint32)0U << 26U) /* SOMI[2] */ | (uint32)((uint32)0U << 27U); /* SOMI[3] */

/** – SPI5 Port open drain enable */ spiREG5->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 18U) /* SIMO[2] */ | (uint32)((uint32)0U << 19U) /* SIMO[3] */ | (uint32)((uint32)0U << 25U) /* SOMI[1] */ | (uint32)((uint32)0U << 26U) /* SOMI[2] */ | (uint32)((uint32)0U << 27U); /* SOMI[3] */

/** – SPI5 Port pullup / pulldown selection */ spiREG5->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 18U) /* SIMO[2] */ | (uint32)((uint32)1U << 19U) /* SIMO[3] */ | (uint32)((uint32)1U << 25U) /* SOMI[1] */ | (uint32)((uint32)1U << 26U) /* SOMI[2] */ | (uint32)((uint32)1U << 27U); /* SOMI[3] */

/** – SPI5 Port pullup / pulldown enable*/ spiREG5->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 18U) /* SIMO[2] */ | (uint32)((uint32)0U << 19U) /* SIMO[3] */ | (uint32)((uint32)0U << 25U) /* SOMI[1] */ | (uint32)((uint32)0U << 26U) /* SOMI[2] */ | (uint32)((uint32)0U << 27U); /* SOMI[3] */

/* SPI5 set all pins to functional */ spiREG5->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ | (uint32)((uint32)1U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 18U) /* SIMO[2] */ | (uint32)((uint32)1U << 19U) /* SIMO[3] */ | (uint32)((uint32)1U << 25U) /* SOMI[1] */ | (uint32)((uint32)1U << 26U) /* SOMI[2] */ | (uint32)((uint32)1U << 27U); /* SOMI[3] */

/** – Initialize TX and RX data buffer Status */ g_spiPacket_t[4U].tx_data_status = SPI_READY; g_spiPacket_t[4U].rx_data_status = SPI_READY;

/** – Finally start SPI5 */ spiREG5->GCR1 = (spiREG5->GCR1 & 0xFEFFFFFFU) | 0x01000000U;

/* USER CODE BEGIN (3) *//* USER CODE END */}

HET配置如下：

void hetInit(void){ /** @b initialize @b HET */

/** – Set HET pins default output value */ hetREG1->DOUT = (uint32)((uint32)0U << 31U) | (uint32)((uint32)0U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)0U << 28U) | (uint32)((uint32)0U << 27U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 15U) | (uint32)((uint32)0U << 14U) | (uint32)((uint32)0U << 13U) | (uint32)((uint32)0U << 12U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 7U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U);

/** – Set HET pins direction */ hetREG1->DIR = (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00008000U | (uint32) 0x00004000U | (uint32) 0x00000000U | (uint32) 0x00001000U | (uint32) 0x00000800U | (uint32) 0x00000400U | (uint32) 0x00000200U | (uint32) 0x00000100U | (uint32) 0x00000080U | (uint32) 0x00000040U | (uint32) 0x00000020U | (uint32) 0x00000010U | (uint32) 0x00000008U | (uint32) 0x00000004U | (uint32) 0x00000002U | (uint32) 0x00000000U;

/** – Set HET pins open drain enable */ hetREG1->PDR = (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U;

/** – Set HET pins pullup/down enable */ hetREG1->PULDIS = (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U;

/** – Set HET pins pullup/down select */ hetREG1->PSL = (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U;

/** – Set HET pins high resolution share */ hetREG1->HRSH = (uint32) 0x00008000U | (uint32) 0x00004000U | (uint32) 0x00002000U | (uint32) 0x00001000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000002U | (uint32) 0x00000000U;

/** – Set HET pins AND share */ hetREG1->AND = (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U;

/** – Set HET pins XOR share */ hetREG1->XOR = (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U;

/* USER CODE BEGIN (1) */

/* USER CODE END */

/** – Setup prescaler values * – Loop resolution prescaler * – High resolution prescaler */ hetREG1->PFR = (uint32)((uint32) 6U << 8U) | ((uint32) 0U);

/** – Parity control register * – Enable/Disable Parity check */ hetREG1->PCR = (uint32) 0x00000005U;

/** – Fill HET RAM with opcodes and Data */ /** – "x" in "HET_INITx_PST" denote the HET module Instance * Valid range of x – 0 to 9 * For HET1 module x = 0 * Refer HET assembler User guide for more Info */ /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 <APPROVED> "HET RAM Fill from the table – Allowed as per MISRA rule 11.2" */ /*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table – Allowed as per MISRA rule 11.2" */ /*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table – Allowed as per MISRA rule 11.2" */ (void)memcpy((void*)hetRAM1, (void*)HET_INIT0_PST, sizeof(HET_INIT0_PST));

/** – Setup interrupt priority level */ hetREG1->PRY = 0xFFFFFFFF;

/** – Enable interrupts */ hetREG1->INTENAC = 0xFFFFFFFFU; hetREG1->INTENAS = (uint32) 0x80000000U | (uint32) 0x40000000U | (uint32) 0x20000000U | (uint32) 0x10000000U | (uint32) 0x08000000U | (uint32) 0x04000000U | (uint32) 0x02000000U | (uint32) 0x01000000U | (uint32) 0x00800000U | (uint32) 0x00400000U | (uint32) 0x00200000U | (uint32) 0x00100000U | (uint32) 0x00080000U | (uint32) 0x00040000U | (uint32) 0x00020000U | (uint32) 0x00010000U | (uint32) 0x00008000U | (uint32) 0x00004000U | (uint32) 0x00002000U | (uint32) 0x00001000U | (uint32) 0x00000800U | (uint32) 0x00000400U | (uint32) 0x00000200U | (uint32) 0x00000100U | (uint32) 0x00000080U | (uint32) 0x00000040U | (uint32) 0x00000020U | (uint32) 0x00000010U | (uint32) 0x00000008U | (uint32) 0x00000004U | (uint32) 0x00000000U | (uint32) 0x00000001U;

/** – Setup control register * – Enable output buffers * – Ignore software breakpoints * – Master or Slave Clock Mode * – Enable HET */ hetREG1->GCR = ( 0x00000001U | (uint32)((uint32)0U << 24U) | (uint32)((uint32)1U << 16U) | (0x00020000U));

/* USER CODE BEGIN (4) *//* USER CODE END */

}

其中红色标注部分若屏蔽掉，则SPI功能正常，若不屏蔽则SPI与HET有冲突

lechi zhang：

回复 Susan Yang:

您好，我的问题已解决。

解决方法：之前在配置SPI时，有部分引脚与HET复用（选择的功能为N2HET）如：

E18
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]

；

B4
N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV

；

N1
N2HET1[15]//MIBSPI1NCS[4]/N2HET2[22]/ECAP1

，SPI配置中该引脚不使用，未使能也未输出。引脚类型选择的时SPI模式。

现在将这些引脚改为GIO模式后，我之前描述的现象就不存在了。

我之前先进行spiInit();测试SPI功能正常，在进行hetInit()，测试HET功能正常。之后再进行SPI测试后，功能就异常了。如果再进行spiInit();功能依然不正常。如果是该引脚类型（与HET复用的引脚，就算配置为HET功能，在SPI中也要配置为GIO模式）引起了该冲突的话，那按道理来说，我再次进行spiInit()后，我的SPI功能就应该恢复正常啊，为何会出现我之前描述的此类现象。是否为芯片级的BUG？

Susan Yang：

回复 lechi zhang:

很高兴您能解决问题！

关于您提到的引脚复用问题，建议您看一下 www.ti.com.cn/…/spnu562a.pdf

的

I/O Multiplexing and Control Module (IOMM)

Susan Yang：

回复 lechi zhang:

以及 6.7.13 PINMMRnn: Input Pin Multiplexing Control Registers 和 6.7.12 PINMMRnn: Output Pin Multiplexing Control Registers

RM57L843 spi与HET初始化冲突问题

Susan Yang：

lechi zhang：

lechi zhang：

lechi zhang：

Susan Yang：

Susan Yang：

相关推荐

热门标签

热门文章

QQ咨询

回顶部