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F28035 移相PWM刚启动瞬间驱动波重合问题

2017-08-25 分类：C2000™ 32位实时 MCU 阅读(346)

F28035做移相全桥，PWM1和PWM2。图上红色是PWM1A，黄色是PWM2B。刚启动时候，PWM1A第一个波形和PWM2B重合？刚启动，这时候，移相重合角为0，不应该重合啊，怎么回事呢？

下面附上初始化程序和启动配置：看我配置有问题吗？

初始化配置：

void Init_EPwm1(void) {
InitEPwm1Gpio();

EPwm1Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm1Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty for EPWM1Ai
EPwm1Regs.CMPB = 0;
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0x0000; // Clear counter

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1Ai
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm1Regs.DBFED = 90; // FED = 50 TBCLKs initially
EPwm1Regs.DBRED = 90; // RED = 70 TBCLKs initially
}

void Init_EPwm2(void) {

InitEPwm2Gpio();
EPwm2Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm2Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty EPWM2Ai
EPwm2Regs.CMPB = 0;
EPwm2Regs.TBPHS.half.TBPHS = PHASE_DEGREE; // Set Phase register to zero initially
EPwm2Regs.TBCTR = 0x0000; // Clear counter

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
// EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // set actions for EPWM2Ai
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;

EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm2Regs.DBFED = 90; // FED = 30 TBCLKs initially // 死区120/1500=0.08
EPwm2Regs.DBRED = 90; // RED = 40 TBCLKs initially

}

启动PWM：

EALLOW; //清除强制拉低,启动PWM时钟

EPwm1Regs.TBCTR=0x0000;

EPwm2Regs.TBCTR = 0x0000;
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

user5089339：

也就是发的第一个驱动波形，没有移动相位。

可是我使能发波，是配置好后的啊？为什么呢

F28035做移相全桥，PWM1和PWM2。图上红色是PWM1A，黄色是PWM2B。刚启动时候，PWM1A第一个波形和PWM2B重合？刚启动，这时候，移相重合角为0，不应该重合啊，怎么回事呢？

下面附上初始化程序和启动配置：看我配置有问题吗？

初始化配置：

void Init_EPwm1(void) {
InitEPwm1Gpio();

EPwm1Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm1Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty for EPWM1Ai
EPwm1Regs.CMPB = 0;
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0x0000; // Clear counter

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1Ai
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm1Regs.DBFED = 90; // FED = 50 TBCLKs initially
EPwm1Regs.DBRED = 90; // RED = 70 TBCLKs initially
}

void Init_EPwm2(void) {

InitEPwm2Gpio();
EPwm2Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm2Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty EPWM2Ai
EPwm2Regs.CMPB = 0;
EPwm2Regs.TBPHS.half.TBPHS = PHASE_DEGREE; // Set Phase register to zero initially
EPwm2Regs.TBCTR = 0x0000; // Clear counter

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
// EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // set actions for EPWM2Ai
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;

EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm2Regs.DBFED = 90; // FED = 30 TBCLKs initially // 死区120/1500=0.08
EPwm2Regs.DBRED = 90; // RED = 40 TBCLKs initially

}

启动PWM：

EALLOW; //清除强制拉低,启动PWM时钟

EPwm1Regs.TBCTR=0x0000;

EPwm2Regs.TBCTR = 0x0000;
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

Brian Wang0：

回复 user5089339:

能否考虑发波前占空比（对应比较值）赋初值或进行限幅处理？

F28035做移相全桥，PWM1和PWM2。图上红色是PWM1A，黄色是PWM2B。刚启动时候，PWM1A第一个波形和PWM2B重合？刚启动，这时候，移相重合角为0，不应该重合啊，怎么回事呢？

下面附上初始化程序和启动配置：看我配置有问题吗？

初始化配置：

void Init_EPwm1(void) {
InitEPwm1Gpio();

EPwm1Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm1Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty for EPWM1Ai
EPwm1Regs.CMPB = 0;
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0x0000; // Clear counter

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1Ai
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm1Regs.DBFED = 90; // FED = 50 TBCLKs initially
EPwm1Regs.DBRED = 90; // RED = 70 TBCLKs initially
}

void Init_EPwm2(void) {

InitEPwm2Gpio();
EPwm2Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm2Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty EPWM2Ai
EPwm2Regs.CMPB = 0;
EPwm2Regs.TBPHS.half.TBPHS = PHASE_DEGREE; // Set Phase register to zero initially
EPwm2Regs.TBCTR = 0x0000; // Clear counter

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
// EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // set actions for EPWM2Ai
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;

EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm2Regs.DBFED = 90; // FED = 30 TBCLKs initially // 死区120/1500=0.08
EPwm2Regs.DBRED = 90; // RED = 40 TBCLKs initially

}

启动PWM：

EALLOW; //清除强制拉低,启动PWM时钟

EPwm1Regs.TBCTR=0x0000;

EPwm2Regs.TBCTR = 0x0000;
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

user5089339：

回复 Brian Wang0:

占空比限值，我也试过，如果这对PWM占空比限了，另外一对就大了。

F28035做移相全桥，PWM1和PWM2。图上红色是PWM1A，黄色是PWM2B。刚启动时候，PWM1A第一个波形和PWM2B重合？刚启动，这时候，移相重合角为0，不应该重合啊，怎么回事呢？

下面附上初始化程序和启动配置：看我配置有问题吗？

初始化配置：

void Init_EPwm1(void) {
InitEPwm1Gpio();

EPwm1Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm1Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty for EPWM1Ai
EPwm1Regs.CMPB = 0;
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0x0000; // Clear counter

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1Ai
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm1Regs.DBFED = 90; // FED = 50 TBCLKs initially
EPwm1Regs.DBRED = 90; // RED = 70 TBCLKs initially
}

void Init_EPwm2(void) {

InitEPwm2Gpio();
EPwm2Regs.TBPRD = 3000; // Period = EPWM1_TIMER_TBPRD+1 TBCLK counts
EPwm2Regs.CMPA.half.CMPA = 1500; // Set 50% fixed duty EPWM2Ai
EPwm2Regs.CMPB = 0;
EPwm2Regs.TBPHS.half.TBPHS = PHASE_DEGREE; // Set Phase register to zero initially
EPwm2Regs.TBCTR = 0x0000; // Clear counter

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
// EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // set actions for EPWM2Ai
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // set actions for EPWM2Ai
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;

EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// Dead-band is fully enabled

EPwm2Regs.DBFED = 90; // FED = 30 TBCLKs initially // 死区120/1500=0.08
EPwm2Regs.DBRED = 90; // RED = 40 TBCLKs initially

}

启动PWM：

EALLOW; //清除强制拉低,启动PWM时钟

EPwm1Regs.TBCTR=0x0000;

EPwm2Regs.TBCTR = 0x0000;
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

user3900194：请问这个问题，解决了吗，我也碰到这样的情况，刚开始发波时，有重合，希望能赐教，谢谢！

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