TI中文支持网在TI的官网上下载的实例程序，在 CCS3.3版本下编译出错，软件版本（VerSion3.3.83.20）
错误提示信息：
>> Cannot open "Debug.lkf"
实例工程链接地址如下：
http://www-s.ti.com/sc/techlit/sprabe8.zip
Hank Zhao：
你可以参考一下下边帖子中的解决方法：https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/178190
xuefei wan：
回复 Hank Zhao:
http://www.deyisupport.com/question_answer/microcontrollers/c2000/f/56/t/14040.aspx
按照上面链接的内容，替换C2400后，问题解决
xuefei wan：
回复 xuefei wan:
>> cannot allocate .text in B0 (page 1)>> warning: entry point other than _c_int0 specified>> errors in input – FL_RD.out not built
编译出现了另外一个错误，
cannot allocate .text in B0 (page 1)
cmd 文件如下：
/* F206 TRIPLE READ */-e START-m FL_RD.map-o FL_RD.out
MEMORY{ PAGE 0 : TB0: origin = 0h, length = 0F0h PSA: origin = 0F0h, length = 0Fh B0: origin = 0FE00h, length = 0100h FLASH0: origin = 0100h, length = 04F00h FLASH1: origin = 05000h, length = 05000h
PAGE 1 : RAMB2: origin = 0060h, length = 0020h RAMB0: origin = 0200h, length = 0100h RAMB1: origin = 0300h, length = 0100h FLASH2: origin = 01000h, length = 01000h} SECTIONS{ .text > B0 PAGE0 .bss > RAMB2 PAGE1 }已经分配了B0 PAGE0，为什么不能分配到page0。
Hank Zhao：
回复 xuefei wan:
B0的长度也太短了，你的.text段的长度肯定不至0xF0吧。
xuefei wan：
回复 Hank Zhao:
这个程序是TI 官方网站提供的，是一个小的汇编程序，不是很大。而且是正式文档中说明的。
TRIPLE_RD.ASM
.title "50M21 FLASH READ ARRAY" .length 50 .width 120 .option X************************************************************* FLASH READ ARRAY (FL_RD) ** Additional Subroutine for TMS320F206 Flash Utilities. ** Revision 1.0 ** This program reads the flash memory with three different ** methods as follows: ** Fast read sequential ** Slow read sequential ** XOR read ** Each read method is CHECKSUM'ed for pass or fail. ** This program can be built to read the flash memory of a ** device that had been cleared, erased, programmed with ** a checker board pattern or programmed with a piece of ** code by changing the compiled switch "CS" below. ** ** ** Passed Parameters: ** FL_START Start address of flash range to be cleared.** This address must start on a row start ** boundary. ** FL_END End address of flash range to be cleared. ** This address must end on a row end ** boundary. ** ** Returned Parameter: ** ACC = error code (0 if passed) ** ** This function can be compiled/assembled and used as a ** standalone test or used by the C2XX_BRX.ASM file. ** ** – For Stand alone, use the read_stdalone.cmd to compile ** and link. Note that when using this mode, the compile ** variable PRG2xx must be set to 0 also set the CNF to 1 ** (by using the CCS) before code is downloaded onto the ** target board since the code is supposingly downloaded on ** the on-chip B0 block ** ** – For using with the control module C2XX_BRX.ASM and ** the utility code Sutils20.asm, use the ** C2XX_BRX(_CCS).CMD to compile and link. Note that when ** using this mode, the compile variable PRG2xx must be set ** to 1. The PRG_2XX(W).EXE automatically set the CNF bit ** to 1 before downloading the C2XX_BBX.OUT onto the F206. ** ************************************************************* .def FL_RD .global FL_RD .def _FL_RD .ref PARMS .global _FL_RD, START .include "fl_vars.h" .textPRG2xx .set 1 ;Set to 0 if not used by C2XX_BRX.ASM file** STATISTICS VARIABLESFCSH .set 070h ;FAST CHECKSUM HI WORDFCSL .set 071h ;FAST CHECKSUM LO WORDSCSH .set 072h ;SLOW CHECKSUM HI WORDSCSL .set 073h ;SLOW CHECKSUM LO WORDXCSH .set 074h ;XOR CHECKSUM HI WORDXCSL .set 075h ;XOR CHECKSUM LO WORDCSH .set 076h ;CORRECT CHECKSUM HICSL .set 077h ;CORRECT CHECKSUM LO
CS .set 0 ;No checksum;CS .set 1 ;clear checksum;CS .set 2 ;erase checksum;CS .set 3 ;checker shecksum
ERSSUML .set 0C000h ;erase checksum loERSSUMH .set 0FFFFh ;erase checksum hi
CLRSUML .set 00000h ;clear checksum loCLRSUMH .set 00000h ;clear checksum hi
CKRSUML .set 0E000h ;checker checksum loCKRSUMH .set 0FFFFh ;checker checksum hi
FPTR .set 07Dh ;FLASH READ POINTERRPT_N .set 07Eh ;TEMPORARY FOR REPEAT COUNTTEMP .set 07Fh ;TEMPORARY VARIABLE** ConstantsFUT .set 0 ;Flash0 under Test;FUT .set 1 ;Flash1 under TestFLST0 .set 0 ;start address of Flash0FLEND0 .set 03FFFh ;end address of Flash0FLST1 .set 04000h ;start address of Flash1FLEND1 .set 07FFFh ;end address of Flash1XORMASK .set 03FFFh ;address XOR mask
.page* .sect "FL_RD" LBL FL_RD_FL_RD:START:* ;;<Configure Status Registers>====================================== SETC SXM ;; ENABLE sign extension LDP #0 LACL #0 ;ACC = 0 SACL SCSL ;INITIALIZE CHECKSUM SACL SCSH ;INITIALIZE CHECKSUM SACL XCSL ;INITIALIZE CHECKSUM SACL XCSH ;INITIALIZE CHECKSUM
.if CS==1 ;CLEAR SPLK #CLRSUML,CSL ;INITIALIZE CHECKSUM SPLK #CLRSUMH,CSH ;INITIALIZE CHECKSUM .endif
.if CS==2 ;ERASE SPLK #ERSSUML,CSL ;INITIALIZE CHECKSUM SPLK #ERSSUMH,CSH ;INITIALIZE CHECKSUM .endif
.if CS==3 ;CHECKER SPLK #CKRSUML,CSL ;INITIALIZE CHECKSUM SPLK #CKRSUMH,CSH ;INITIALIZE CHECKSUM .endif
.if PRG2xx CALL RD3 ;Execute Triple Read on Flash0/1 LDP #PARMS RET .else
SPLK #FLST0,FL_START ;set flash start adrs SPLK #FLEND0,FL_END ;set flash end adrs LAR AR5,FL_START ;AR5 indicates which flash CALL RD3 ;Execute Triple Read on Flash0
BCND FailRD3_0,NEQ ;if Flash0 fails
LACL #0 ;ACC = 0 SACL SCSL ;INITIALIZE CHECKSUM SACL SCSH ;INITIALIZE CHECKSUM SACL XCSL ;INITIALIZE CHECKSUM SACL XCSH ;INITIALIZE CHECKSUM
SPLK #FLST1,FL_START ;set flash start adrs SPLK #FLEND1,FL_END ;set flash end adrs LAR AR5,FL_START ;AR5 indicates which flash CALL RD3 ;Execute Triple Read on Flash0
BCND FailRD3_1,NEQ ;if Flash1 fails
LBL PASS NOP* B PASS B FL_RD ;looping
LBL FailRD3_0 IDLE B FailRD3_0 LBL FailRD3_1 IDLE B FailRD3_1
.endif
** EXECUTE FAST CHECKSUM* LBL RD3 MAR *,AR5 ;ARP=>AR5 LAR AR0,#0 LACL FL_END ;ACC = FLASH END +1 SUBS FL_START ;ACC= FLASH LENGTH +1* SUB #1 ;ACC -= 1 FLASH LENGTH SACL RPT_N ;SAVE FOR REPEAT COUNT SPLK #1,TEMP ;MPY FACTOR FOR CHECKSUM MPYK #0 ;PREG=0 LACL #0 ;ACC=0 CMPR 3 BCND OverFL0,TC RPT RPT_N ;FOR I=0;I<N;++ MAC #FLST0,TEMP ;CHECKSUM MEMORY B OverFL1 LBL OverFL0 nop RPT RPT_N ;FOR I=0;I<N;++ MAC #FLST1,TEMP ;CHECKSUM MEMORY
LBL OverFL1 APAC ; LAST SUM SACL FCSL ;SAVE LO CHECKSUM SACH FCSH ;SAVE HI CHECKSUM** EXECUTE SLOW CHECKSUM* LAR AR1,FL_START ;SET START ADRS LAR AR0,FL_END ;SET END ADRS MAR *,AR0 MAR *+,AR1 LACL FL_END ;ACC=>END OF ARRAY + 1 ADD #1* LBL SLOOP SUB #1 ;ACC=>NEXT WORD SACL FPTR ;SAVE POINTER TBLR TEMP ;DUMMY READ OF FLASH DATA TBLR TEMP ;SLOW READ OF FLASH DATA LACC SCSH,16 ;ACCH=SLOW CHECKSUM HI ADDS SCSL ;ACC = SLOW CHECKSUM ADD TEMP ;ACC += NEXT FLASH WORD SACL SCSL ;SAVE SLOW CHECKSUM LO SACH SCSH ;SAVE SLOW CHECKSUM HI LACL FPTR ;ACC=>CURRENT WORD* MAR *+ ;AR1=+1 CMPR 3 ;IF AR1 != AR0 BCND SLOOP,TC ;THEN CONTINUE LOOP* ; ELSE DONE SLOW CHECKSUM** EXECUTE XOR CHECKSUM* SPLK #XORMASK,XOR ;initialize XOR LAR AR1,FL_START ;SET START ADRS LACL FL_END ;ACC=>END OF ARRAY + 1 ADD #1* LBL XLOOP SUB #1 ;ACC=>NEXT WORD SACL FPTR ;SAVE POINTER XOR XOR ;SWITCH TO XOR PATTERN TBLR TEMP ;DUMMY READ OF FLASH DATA XOR XOR ;RESTORE ADRS TO CURRENT WORD TBLR TEMP ;SLOW READ OF FLASH DATA LACC XCSH,16 ;ACCH=SLOW CHECKSUM HI ADDS XCSL ;ACC = SLOW CHECKSUM ADD TEMP ;ACC += NEXT FLASH WORD SACL XCSL ;SAVE SLOW CHECKSUM LO SACH XCSH ;SAVE SLOW CHECKSUM HI LACL FPTR ;ACC=>CURRENT WORD* MAR *+ ;AR1=+1 CMPR 3 ;IF AR1 != AR0 BCND XLOOP,TC ;THEN CONTINUE LOOP* ; ELSE DONE SLOW CHECKSUM** COMPARE CHECKSUMS* MAR *,AR1 ;ARP=>AR1 .if CS==0 LAR AR0,FCSH ;AR0=MASTER CHECKSUM .else LAR AR0,CSH ;AR0=MASTER CHECKSUM .endif
LAR AR1,FCSH ;AR1=FAST CHECKSUM HI CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,SCSH ;AR1=FAST CHECKSUM HI CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,XCSH ;AR1=FAST CHECKSUM HI CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP .if CS==0 LAR AR0,FCSL ;AR0=MASTER CHECKSUM .else LAR AR0,CSL ;AR0=MASTER CHECKSUM .endif LAR AR1,FCSL ;AR1=FAST CHECKSUM LO CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,SCSL ;AR1=FAST CHECKSUM LO CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,XCSL ;AR1=FAST CHECKSUM LO CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP* LACL #0 ;NO ERRORS RET ;RETURN TO CALLING SEQUENCE* LBL CS_ERROR LACL #0Ch ;CHECKSUM FAILS RET ;RETURN TO CALLING SEQUENCE* .end
*************************************************************** Delay And Access Mode Subroutines *** *** TMS320F2XX Flash Utilities. *** Revision: 2.0, 9/10/97 *** Revision: 2.1, 1/31/98 *** *** Filename: sutils20.asm *** Modified for F2xx : Sam Saba 12/24/96 *** Changes20: Changed DELAY parameter passing to use AR6 *** instead of a RAM location. *** Changes21: Added conditional assembly statements to REGS *** and ARRAY subroutines for F206 versus F24X. *** *** *** Called by: These utilites are used by CLEAR,ERASE, *** PROGRAM algorithms written for F2xx devices. *** Function : DELAY – Delay loop specified by AR6. *** REGS – Clears MODE bit of F_ACCESS0/1 to *** access flash module control registers.*** ARRAY – Sets MODE bit of F_ACCESS0/1 to access*** the flash array. *************************************************************** .include "svar20.h" .def DELAY,REGS,ARRAYF24X .set 0 .sect "DLY"
**************************************Delays as follows: ** LAR AR6,#N 2 Cycles ** CALL DELAY 4 Cycles ** RPT #DLOOP 2*(N+1) Cycles ** NOP DLOOP*(N+1) Cycles ** BANZ DLY_LP 4*N+2 Cycles ** RET 4 Cycles ** ———————— ** = DLOOP(N+1)+6*N+14 Cycles ** Set N and DLOOP appropriately to ** get desired delay. **************************************
DELAY ;AR6 = OUTER LOOP COUNTDLY_LP RPT #DLOOP ;APPROX 5US DELAY NOP BANZ DLY_LP,*- ;LOOP UNTIL DONE RET ;RETURN TO CALLING SEQUENCE
.page*************************************************** REGS – Clears MODE bit of F_ACCESS0/1 to *** access flash module control registers.**************************************************** .sect "REG"REGS SPLK #0000h,SPAD2***********The next instruction is for F240 only,************* .if F24X != 0 ;Assemble for F24X only. OUT SPAD2,F24X_ACCS ;Enable F24X flash reg mode. ;SPAD1 is dummy value. .endif
************************************************************** .if F24X = 0 ;Assemble for F206 only. LACC FL_ST SUB #4000h BCND reg1, geq ;if address>= 4000h,set ;set reg mode for flash1 array OUT SPAD2,F_ACCESS0 ;Change mode of flash0. RETreg1 OUT SPAD2,F_ACCESS1 ;Change mode of flash1. .endif RET ;RETURN TO CALLING SEQUENCE
.page*************************************************** ARRAY – Sets MODE bit of F_ACCESS0/1 to access*** the flash array. **************************************************** .sect "ARY"ARRAY SPLK #0001h,SPAD2***********The next instruction is for F240 only,************* .if F24X != 0 ;Assemble for F24X only. IN SPAD1,F24X_ACCS ;Enable F24X flash array mode. ;SPAD1 is dummy value. .endif
************************************************************** .if F24X = 0 ;Assemble for F206 only. LACC FL_ST SUB #4000h BCND ary1, geq ;if address>= 4000h,set ;set reg mode for flash1 array OUT SPAD2,F_ACCESS0 ;Change mode of flash0. RETary1 OUT SPAD2,F_ACCESS1 ;Change mode of flash1. .endif RET ;RETURN TO CALLING SEQUENCE .end
Hank Zhao：
回复 xuefei wan:
你查看一下生成的.map文件，先确定一下实际生成的text段有多大？
xuefei wan：
回复 Hank Zhao:
.MAP文件如下，看上去没有超过0100h的范围，我是第一次使用ccs，还请多指点。
******************************************************************************TMS320C24xx COFF Linker Version 7.04 ******************************************************************************>> Linked Wed May 11 14:39:05 2016
OUTPUT FILE NAME: <FL_RD.out>ENTRY POINT SYMBOL: "START" address: 00000142
MEMORY CONFIGURATION
name origin length used attributes fill ——– ——– ——— ——– ———- ——–PAGE 0: TB0 00000000 0000000f0 000000e9 RWIX PSA 000000f0 00000000f 0000000d RWIX FLASH0 00000100 000004f00 000000ad RWIX FLASH1 00005000 000005000 00000000 RWIX B0 0000fe00 000000100 00000000 RWIX
PAGE 1: RAMB2 00000060 000000020 00000000 RWIX RAMB0 00000200 000000100 00000000 RWIX RAMB1 00000300 000000100 00000000 RWIX FLASH2 00001000 000001000 00000000 RWIX
SECTION ALLOCATION MAP
output attributes/section page origin length input sections——– —- ———- ———- —————-.text 1 00000000 00000000 UNINITIALIZED 00000000 00000000 C2XX_BRX.obj (.text) 00000000 00000000 TRIPLE_RD.obj (.text) 00000000 00000000 SUTILS20.obj (.text)
PAGE1 1 00000000 00000000 UNINITIALIZED
.bss 1 00000060 00000000 UNINITIALIZED 00000060 00000000 C2XX_BRX.obj (.bss) 00000060 00000000 TRIPLE_RD.obj (.bss) 00000060 00000000 SUTILS20.obj (.bss)
PAGE1 1 00000000 00000000 UNINITIALIZED
.data 1 00000000 00000000 UNINITIALIZED 00000000 00000000 C2XX_BRX.obj (.data) 00000000 00000000 TRIPLE_RD.obj (.data) 00000000 00000000 SUTILS20.obj (.data)
PRG_parm 0 00000000 0000000c 00000000 0000000c C2XX_BRX.obj (PRG_parm)
PRG_data 0 0000000c 000000c8 0000000c 000000c8 C2XX_BRX.obj (PRG_data)
ary_var 0 000000d4 00000010 000000d4 00000010 C2XX_BRX.obj (ary_var)
PRG_text 0 00000100 00000035 00000100 00000035 C2XX_BRX.obj (PRG_text)
DLY 0 000000e4 00000005 000000e4 00000005 SUTILS20.obj (DLY)
REG 0 000000f0 0000000d 000000f0 0000000d SUTILS20.obj (REG)
ARY 0 00000135 0000000d 00000135 0000000d SUTILS20.obj (ARY)
FL_RD 0 00000142 0000006b 00000142 0000006b TRIPLE_RD.obj (FL_RD)
GLOBAL SYMBOLS
address name address name——– —- ——– —-00000060 .bss 00000000 PARMS00000000 .data 00000000 .text00000000 .text 00000000 PRG_bufaddr00000135 ARRAY 00000000 etext000000e4 DELAY 00000000 edata00000142 FL_RD 00000000 .data00000000 PARMS 00000001 PRG_bufsize00000000 PRG_bufaddr 00000002 PRG_devsize00000001 PRG_bufsize 00000003 PRG_options00000002 PRG_devsize 00000004 PRG_paddr00000126 PRG_erase 00000005 PRG_page00000100 PRG_init 00000006 PRG_length00000006 PRG_length 00000007 PRG_status00000003 PRG_options 00000009 PROTECT00000004 PRG_paddr 0000000a SEG_ST00000005 PRG_page 0000000b SEG_END00000105 PRG_program 00000060 end00000007 PRG_status 00000060 .bss00000130 PRG_stop 000000e4 DELAY0000012b PRG_verify 000000f0 REGS00000009 PROTECT 00000100 PRG_init000000f0 REGS 00000105 PRG_program0000000b SEG_END 00000126 PRG_erase0000000a SEG_ST 0000012b PRG_verify00000142 START 00000130 PRG_stop00000142 _FL_RD 00000135 ARRAYUNDEFED _c_int0 00000142 FL_RDffffffff cinit 00000142 START00000000 edata 00000142 _FL_RD00000060 end ffffffff pinit00000000 etext ffffffff cinitffffffff pinit UNDEFED _c_int0
[32 symbols]
Hank Zhao：
回复 xuefei wan:
下边这几段代码的obj加起来已经超过0xF0了，所以你需要增大B0的长度。
PRG_parm 0 00000000 0000000c 00000000 0000000c C2XX_BRX.obj (PRG_parm)
PRG_data 0 0000000c 000000c8 0000000c 000000c8 C2XX_BRX.obj (PRG_data)
ary_var 0 000000d4 00000010 000000d4 00000010 C2XX_BRX.obj (ary_var)
PRG_text 0 00000100 00000035 00000100 00000035 C2XX_BRX.obj (PRG_text)
DLY 0 000000e4 00000005 000000e4 00000005 SUTILS20.obj (DLY)
REG 0 000000f0 0000000d 000000f0 0000000d SUTILS20.obj (REG)
ARY 0 00000135 0000000d 00000135 0000000d SUTILS20.obj (ARY)
FL_RD 0 00000142 0000006b 00000142 0000006b TRIPLE_RD.obj (FL_RD)
xuefei wan：
回复 Hank Zhao:
您好：
我是这将b0修改为内部saram，SARAM 的大小为4K ，我设定了1K的长度，但是编译后，还是看不到数据分配。
B0: origin = 08000h, length = 0400h
/* F206 TRIPLE READ */-e START-m FL_RD.map-o FL_RD.out
MEMORY{ PAGE 0 : TB0: origin = 0h, length = 0F0h PSA: origin = 0F0h, length = 0Fh FLASH0: origin = 0100h, length = 04F00h FLASH1: origin = 05000h, length = 03000h
PAGE 1 : RAMB2: origin = 0060h, length = 0020h RAMB0: origin = 0200h, length = 0100h RAMB1: origin = 0300h, length = 0100h FLASH2: origin = 01000h, length = 01000h B0: origin = 08000h, length = 0400h} SECTIONS{ .text > B0 PAGE1 .bss > RAMB2 PAGE1 }
Hank Zhao：
回复 xuefei wan:
你需要将“B0: origin = 08000h, length = 0400h”放在PAGE 0:中，重新编译后，CCS的报错是什么？
