TI中文支持网各位专家，请问MSP430F249 的外部晶振在复位后默认是开启的吗？如不不是的话，为什么用GERACE生成的代码中为什么是这样的：
void BCSplus_graceInit(void)
{
/* USER CODE START (section: BCSplus_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: BCSplus_graceInit_prologue) */
/* * Basic Clock System Control 2
* * SELM_2 — XT2CLK/LFXTCLK
* DIVM_0 — Divide by 1
* SELS — XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when XT2 oscillator not present
* DIVS_0 — Divide by 1
* ~DCOR — DCO uses internal resistor
* * Note: ~DCOR indicates that DCOR has value zero
*
*/
BCSCTL1 &= ~XT2OFF;
BCSCTL2 = SELM_2 | DIVM_0 | SELS | DIVS_0;
if (CALBC1_8MHZ != 0xFF) {
/* Adjust this accordingly to your VCC rise time */
__delay_cycles(100000);
// Follow recommended flow. First, clear all DCOx and MODx bits. Then
// apply new RSELx values. Finally, apply new DCOx and MODx bit values.
DCOCTL = 0x00;
BCSCTL1 = CALBC1_8MHZ; /* Set DCO to 8MHz */
DCOCTL = CALDCO_8MHZ;
}
/* * Basic Clock System Control 1
* * ~XT2OFF — Enable XT2CLK
* ~XTS — Low Frequency
* DIVA_0 — Divide by 1
* * Note: ~<BIT> indicates that <BIT> has value zero
*/
BCSCTL1 |= DIVA_0;
/* USER CODE START (section: BCSplus_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: BCSplus_graceInit_epilogue) */
}，以上代码中没有等待外部晶振稳定的代码，像自己写F149的时钟初始化中要用到
do {
IFG1 &= ~OFIFG; // Clear OSC Fault flag
__delay_cycles(50000); // Time for flag to set again
} while (IFG1 & OFIFG); // Loop while OSC Fault flag is set
还请各位专家解释一下
Hardy Hu：
XT1由XTS控制频率范围，LFXT1Sx控制是否启用，上电复位后默认是选择XT1为32768HZ晶体或时钟源；
XT2由XT2OFF控制开启与关闭，上电复位后是开启的。
其他时钟系统配置请详见MSP430x2xx Family User's Guide (Rev. I) chapter 5 Basic Clock Module+
xueyao han：
回复 Hardy Hu:
我又看了一下，XT2默认是关闭的，所以在GRACE产生的初始化代码中有BCSCTL1 &= ~XT2OFF这个语句，但是后面直接就跟了
BCSCTL2 = SELM_2 | DIVM_0 | SELS | DIVS_0; 把MCLK切换到了XT2，没有任何的延时语句，这样的话晶振还没震起来，马上就切换，不会出问题吗？不用再像F149那样写个延时函数，判断当晶振稳定后，再转换吗？
