TI中文支持网我想用DCO + FLL来得到较为稳定的5MHz，所以设置了一下寄存器：
{
P5SEL |= BIT4 + BIT5; // Port select XT1
REFCTL0 &= ~REFMSTR;
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
}while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag
// Initialize DCO to 5MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
__bic_SR_register(SCG0); // Enable the FLL control loop
// 32 x 32 x 5 MHz / 32,768 Hz = 156250= MCLK cycles for DCO to settle
__delay_cycles(156250);
Hardy Hu：
你好！
下面这一段代码是将XT1的32768HZ倍频到2MHZ的示例，请参考。
// Configuration: XT1 = 32768HZ, ACLK = 32768HZ, MCLK = SMCLK = 2MHz
UCSCTL2 = FLLD_0 + FLLN5_L + FLLN4_L + FLLN3_L + FLLN2_L ; // FLL output = XT1CLK * 61 UCSCTL3 = SELREF__XT1CLK; // Select XTCLK as the FLL source UCSCTL4 = SELA__XT1CLK + SELS__DCOCLK + SELM__DCOCLK; // ACLK = XT1CLK, MCLK = SMCLK = DCOCLK UCSCTL6 = XT2OFF + XT1DRIVE_0 + XCAP_3; // XT2OFF, XCAP 12pf UCSCTL6 &= ~XT1OFF; // XT1ON
