时钟初始化代码如下:
发现进入LPM1,过几分钟后MOD和DCO的值发生了变化,导致串口的波特率不匹配(115200)。
实测波特率降低到了80K左右
有什么办法解决吗?
static bool_t bsp_clock_init(void) {
//32768 XT1
//MAIN CLOCK 12MHz
//SACLK 32.768K
//SMCLK 12MHz
P5SEL |= BIT4 + BIT5; // CLOCK
// Set DCO FLL reference = XT1 and n=1
UCSCTL3 = FLLREFDIV_0 + SELREF__XT1CLK;
// Set ACLK = XT1 SMCLK=MCLK=12MHz
UCSCTL4 = SELM__DCOCLKDIV + SELS__DCOCLKDIV + SELA__XT1CLK;
// Increase Vcore setting to level1 to support fsystem=12MHz
// NOTE: Change core voltage one level at a time..
set_vcore_up(0x01);
// Initialize DCO to 12MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2 D=2 N=374 n=1
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do {
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1 & OFIFG); // Test oscillator fault flag
return true;
}
Terry Deng:
建议用MSPware里面的例程运行看看,应该不会有这样问题
Ling Zhu2:
因为 LPM1 的时候 FLL 关掉了
灰小子:
回复 Ling Zhu2:
进入低功耗模式,不建议再让msp430执行任务了。建议退出低功耗模式再执行