MSP430F5529 ADC

#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  ADC12CTL0 = ADC12SHT02 + ADC12ON;         // Sampling time, ADC12MEM5
  ADC12CTL1 = ADC12SHP;                     // Use sampling timer
  ADC12IE = BIT0;   ADC12MCTL0 = ADC12INCH_5;// Enable interrupt
  ADC12CTL0 |= ADC12ENC;
  P6SEL |= BIT5;                            // P6.5 ADC option select
  P1DIR |= 0x01;                            // P1.0 output
  P8DIR |= 0x01;
  P8OUT |= 0x01;
  while (1)
  {
    ADC12CTL0 |= ADC12SC;                   // Start sampling/conversion      __bis_SR_register(LPM0_bits + GIE);     // LPM0, ADC12_ISR will force exit
    __no_operation();                       // For debugger
  }
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(ADC12IV,ADC12IV_ADC12IFG15))
  {
  case  ADC12IV_NONE:         break;                           // Vector  0:  No interrupt
  case  ADC12IV_ADC12OVIFG:   break;                           // Vector  2:  ADC overflow
  case  ADC12IV_ADC12TOVIFG:  break;                           // Vector  4:  ADC timing overflow
  case  ADC12IV_ADC12IFG0:                          if (ADC12MEM0 >= 0x7ff)                 // ADC12MEM = A5 > 0.5AVcc?
                            P1OUT |= BIT0;                        // P1.0 = 1
                          else
                            P1OUT &= ~BIT0;                       // P1.0 = 0

                          __bic_SR_register_on_exit(LPM0_bits);                          break;                              // Vector  6:  ADC12IFG0break; // Exit active CPU
  case  ADC12IV_ADC12IFG1: break;                           // Vector  8:  ADC12IFG1
  case  ADC12IV_ADC12IFG2: break;                           // Vector 10:  ADC12IFG2
  case  ADC12IV_ADC12IFG3: break;                           // Vector 12:  ADC12IFG3
  case  ADC12IV_ADC12IFG4: break;                           // Vector 14:  ADC12IFG4
  case  ADC12IV_ADC12IFG5: break;                           // Vector 16:  ADC12IFG5
  case  ADC12IV_ADC12IFG6: break;                           // Vector 18:  ADC12IFG6
  case  ADC12IV_ADC12IFG7: break;                           // Vector 20:  ADC12IFG7
  case  ADC12IV_ADC12IFG8: break;                           // Vector 22:  ADC12IFG8
  case  ADC12IV_ADC12IFG9: break;                           // Vector 24:  ADC12IFG9
  case ADC12IV_ADC12IFG10: break;                           // Vector 26:  ADC12IFG10
  case ADC12IV_ADC12IFG11: break;                           // Vector 28:  ADC12IFG11
  case ADC12IV_ADC12IFG12: break;                           // Vector 30:  ADC12IFG12
  case ADC12IV_ADC12IFG13: break;                           // Vector 32:  ADC12IFG13
  case ADC12IV_ADC12IFG14: break;
  case ADC12IV_ADC12IFG15: break;// Vector 34:  ADC12IFG14
  default: break;  }
}