TI中文支持网Part Number:ADS1120
电路设计如图：
上电配置正常情况时，FPGA可以正确获取负压和温度数据，上电配置命令为0X43 0XB0D04000，正常时波形如图：
异常情况一：上电配置异常时，FPGA不可以正确获取负压和温度数据，异常波形如图：
异常情况二：上电配置波形正常，但是FPGA获取到的负压和温度数据异常
FPGA代码如下：
module ADS1120 (
clk_adc,
SYS_nRESET,
SPI_DIN,
SPI_nDRDY,
SPI_SCK,
SPI_nCS,
SPI_DOUT,
Get_Air_Pres,
Get_Liqud_Pres,
Get_Hemo_Temp,
Get_Dilu_Temp,
ctr_heat,
cnt_debug,
cnt_debug1
);
input clk_adc;
input SYS_nRESET;
input SPI_DIN;
input SPI_nDRDY;
output SPI_SCK;
output SPI_nCS;
output SPI_DOUT;
output [15:0]Get_Air_Pres,Get_Liqud_Pres,Get_Hemo_Temp,Get_Dilu_Temp;
output ctr_heat;
output [3:0]cnt_debug;
output [3:0]cnt_debug1;
//assign SPI_nCS = 1'b0;
reg [3:0]cnt_debug;
wire [15:0]ret_data;
reg [15:0]Get_Air_Pres,Get_Liqud_Pres;
reg [15:0]Get_Hemo_Temp,Get_Dilu_Temp;
reg [7:0]cfg_cmd;reg [31:0]cfg_data;reg [1:0]cnt_fp_2M;
wire clr_cfg_en;
reg cfg_en;
wire spi_busy;
reg spi_busy_d;assign ctr_heat = 1'b0;reg[5:0]state,state_ns;localparam[3:0]
S_PWR_UP =4'd0,
S_ADC_INIT =4'd1,
S_ADC_START =4'd2,
S_IDLE =4'd3,
S_ADC_PRES_AIR =4'd4,
S_RDATA_ADC_AIR =4'd5,
S_ADC_PRES_LIQUD =4'd6,
S_RDATA_ADC_LIQUD =4'd7,
S_ADC_TEMP_HEMO =4'd8,
S_RDATA_ADC_HEMO =4'd9,
S_ADC_TEMP_DILU =4'd10,
S_RDATA_ADC_DILU =4'd11,
S_OVER =4'd12;
always@(posedge clk_adc)
begin
spi_busy_d<=spi_busy;
end
// always@(posedge SYSCLK_12M)
// begin
// if(cnt_fp_2M<2'd2)
// begin
// cnt_fp_2M<=cnt_fp_2M+2'd1;
// end // else // begin // cnt_fp_2M<=2'd0;
// clk_adc<=~clk_adc;
// end// end
/********************************************//**************state machine part1*****************//********************************************/// always@(posedge clk_adc)
// begin
// if(!SYS_nRESET)
// begin
// state <=S_PWR_UP; // end
// else
// begin
// state <=state_ns;
// end
// end
reg [23:0]cnt_dly;
always@(posedge clk_adc)
begin
if(cnt_dly<24'd10000000)
cnt_dly<=cnt_dly+24'd1;
else cnt_dly<=cnt_dly;
end
/********************************************//**********state machine part2***************//************REG Config Mode*****************//********************************************/always@(posedge clk_adc)
begin
if(!SYS_nRESET)
begin
state <=S_PWR_UP; end
else
begin case(state)
S_PWR_UP:
begin if(cnt_dly<24'd10000000)
state<=S_PWR_UP;
else state<=S_ADC_INIT;
end S_ADC_INIT:
begin
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_ADC_START;
end else begin state<=S_ADC_INIT;
end end S_ADC_START:
begin
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_IDLE;
end else begin state<=S_ADC_START;
end end S_IDLE:
begin state<=S_ADC_PRES_AIR;
//state<=S_ADC_PRES_LIQUD;
//state<=S_ADC_TEMP_HEMO;
//state<=S_ADC_TEMP_DILU;
//state<=S_RDATA_ADC_DILU;
end S_ADC_PRES_AIR:
begin //state<=S_RDATA_ADC_AIR;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_RDATA_ADC_AIR;
end else begin state<=S_ADC_PRES_AIR;
end end S_RDATA_ADC_AIR:
begin
//state<=S_ADC_PRES_LIQUD;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_ADC_PRES_LIQUD;
// state<=S_OVER;
end else begin state<=S_RDATA_ADC_AIR;
end end S_ADC_PRES_LIQUD:
begin //state<=S_RDATA_ADC_LIQUD;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_RDATA_ADC_LIQUD;
end else begin state<=S_ADC_PRES_LIQUD;
end end
S_RDATA_ADC_LIQUD:
begin
//state<=S_ADC_TEMP_HEMO;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_ADC_TEMP_HEMO;
// state<=S_OVER;
end else begin state<=S_RDATA_ADC_LIQUD;
end end S_ADC_TEMP_HEMO:
begin //state<=S_RDATA_ADC_HEMO;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_RDATA_ADC_HEMO;
end else begin state<=S_ADC_TEMP_HEMO;
end end S_RDATA_ADC_HEMO:
begin
//state<=S_ADC_TEMP_DILU;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_ADC_TEMP_DILU;
// state<=S_OVER;
end else begin state<=S_RDATA_ADC_HEMO;
end end S_ADC_TEMP_DILU:
begin
//state<=S_OVER;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_RDATA_ADC_DILU;
end else begin state<=S_ADC_TEMP_DILU;
end end S_RDATA_ADC_DILU:
begin
//state<=S_OVER;
if((spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin state<=S_OVER;
end else begin state<=S_RDATA_ADC_DILU;
end end S_OVER:
begin
state<=S_IDLE;
end default:
begin state<=S_IDLE; end endcase
endend
always@(posedge clk_adc)
begin
if((state==S_RDATA_ADC_AIR)&&(spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin
Get_Air_Pres<=ret_data; //
end else if((state==S_RDATA_ADC_LIQUD)&&(spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin
Get_Liqud_Pres<=ret_data;
end
else if((state==S_RDATA_ADC_HEMO)&&(spi_busy_d==1'b1)&&(spi_busy==1'b0))
// else if((state==S_RDATA_ADC_DILU)&&(spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin
Get_Hemo_Temp<=ret_data;
end
else if((state==S_RDATA_ADC_DILU)&&(spi_busy_d==1'b1)&&(spi_busy==1'b0))
// else if((state==S_RDATA_ADC_HEMO)&&(spi_busy_d==1'b1)&&(spi_busy==1'b0))
begin
Get_Dilu_Temp<=ret_data;
end
else begin
Get_Air_Pres<=Get_Air_Pres;
Get_Liqud_Pres<=Get_Liqud_Pres;
Get_Hemo_Temp<=Get_Hemo_Temp;
Get_Dilu_Temp<=Get_Dilu_Temp;
endend
always@(posedge clk_adc)
begin
if((clr_cfg_en==1'b0)&&((state==S_ADC_INIT)||(state==S_ADC_START)
||(state==S_ADC_PRES_AIR)||(state==S_RDATA_ADC_AIR)
||(state==S_ADC_PRES_LIQUD)||(state==S_RDATA_ADC_LIQUD)
||(state==S_ADC_TEMP_HEMO)||(state==S_RDATA_ADC_HEMO)
||(state==S_ADC_TEMP_DILU)||(state==S_RDATA_ADC_DILU)))
begin
cfg_en<=1'b1;
end
else
begin
cfg_en<=1'b0;
end
end
always@(posedge clk_adc)
// always@(*)
begin
if(state==S_IDLE)
begin
cfg_cmd <= 8'd0;
cfg_data <= 32'd0;
end
// else if(state==S_ADC_INIT)
begin
cfg_cmd <= 8'b01000011;
cfg_data <= 32'hB0D04000;
end// else if(state==S_ADC_START)
begin
// cfg_cmd <= 8'b00001000;
// cfg_data <= 32'h00000000;
cfg_cmd <= 8'b00000000;
cfg_data <= 32'h00000000;
end
else if(state==S_ADC_PRES_AIR)
begin
cfg_cmd <= 8'b01000000;
cfg_data <= 32'h00000080;
end//here
else if(state==S_RDATA_ADC_AIR)
begin
cfg_cmd <= 8'b00000000;
cfg_data <= 32'h00000000;
end
else if(state==S_ADC_PRES_LIQUD)
begin
cfg_cmd <= 8'b01000000;
cfg_data <= 32'h00000090;
end
else if(state==S_RDATA_ADC_LIQUD)
begin
cfg_cmd <= 8'b00000000;
cfg_data <= 32'h00000000;
end
else if(state==S_ADC_TEMP_HEMO)
begin
cfg_cmd <= 8'b01000000;
cfg_data <= 32'h000000A0;
end
else if(state==S_RDATA_ADC_HEMO)
begin
cfg_cmd <= 8'b00000000;
cfg_data <= 32'h00000000;
end
else if(state==S_ADC_TEMP_DILU)
begin
cfg_cmd <= 8'b01000000;
cfg_data <= 32'h000000B0;
// cfg_cmd <= 8'b01000011;
// cfg_data <= 32'hB0D44000;
end
else if(state==S_RDATA_ADC_DILU)
begin
cfg_cmd <= 8'b00000000;
cfg_data <= 32'h00000000;
end else begin cfg_cmd <= cfg_cmd;//cfg_cmd;
cfg_data <= cfg_data;//cfg_data;
endend
always@(posedge clk_adc)
begin
if(state==S_PWR_UP)
begin cnt_debug<=4'd0;
end else if(state==S_ADC_INIT)
begin cnt_debug<=4'd1;
end else if(state==S_ADC_START)
begin cnt_debug<=4'd2;
end else if(state==S_IDLE)
begin cnt_debug<=4'd3;
end else if(state==S_ADC_PRES_AIR)
begin cnt_debug<=4'd4;
end else if(state==S_RDATA_ADC_AIR)
begin cnt_debug<=4'd5;
end else if(state==S_ADC_PRES_LIQUD)
begin cnt_debug<=4'd6;
end else if(state==S_RDATA_ADC_LIQUD)
begin cnt_debug<=4'd7;
end else if(state==S_ADC_TEMP_HEMO)
begin cnt_debug<=4'd8;
end else if(state==S_RDATA_ADC_HEMO)
begin cnt_debug<=4'd9;
end else if(state==S_ADC_TEMP_DILU)
begin cnt_debug<=4'd10;
end else if(state==S_RDATA_ADC_DILU)
begin cnt_debug<=4'd11;
end else if(state==S_OVER)
begin cnt_debug<=4'd12;
end else begin cnt_debug<=4'd15;
endend
CFG_SPI ADC_CFG (
.clk_adc(clk_adc),
.SYS_nRESET(SYS_nRESET),
.cfg_en(cfg_en),//keep 1 until config finished;
.cfg_cmd(cfg_cmd),
.cfg_wdata(cfg_data),
.drdy(SPI_nDRDY),
.spi_cs(SPI_nCS),
.spi_sck(SPI_SCK),
.spi_sdo(SPI_DOUT),
.spi_sdi(SPI_DIN),
.spi_busy(spi_busy),
.clr_cfg_en(clr_cfg_en),
.spi_rdata(ret_data),
.cnt_debug1(cnt_debug1)
);
endmodule
请问一下出现上面2种异常情况的可能原因是？
li chunfeng：
麻烦帮忙确认一下出现上面2种情况的可能原因？
