TI中文支持网Part Number:TS3L4892Other Parts Discussed in Thread:TS3L301, TIDEP0036
Hi Team,
We want to connect nBm and An to RJ-45 in our 1G application. What are some PCB layout questions we should consider?"
1. Is there impedance information available?
2. Are there any restrictions on trace length?
3. What should be the maximum allowable length difference between the two lines of a differential signal pair?
Regards,
Nina
Vivian Gao：
Hi
We looked it up for you, unfortunately, for this chip, TI does not give an example of the schematic and Layout. As a rule of thumb, you can do that
1) The power coupling capacitor should be as close as possible to the power supply end, the traces should be as short as possible, and the rated voltage of the capacitor should be sufficient.2) The input signal trace is also as short as possible, reducing parasitic inductance and parasitic capacitance, which will help reduce overshoot and ringing.3) Ground plane treatment, using a ground plane , reduces EMI.4) Differential signal routing, according to 100ohm differential impedance routing, reduce signal reflection.
TS3L301 is a chip of the same category as this chip and TI provides a reference design. You can refer to Design files & products of link below, which may be helpful to you
TIDEP0036 reference design | TI.com
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Nina Chen：
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Nina Chen：
Hi,
I followed the instructions to download the EVM file for TIDEP0036, but I can't open the .brd file using Cadence Allegro Viewer. Could you provide a .brd file that can be opened properly? Thanks.
Regards,
Nina
,
Vivian Gao：
Hi
No other .brd files.
If you still can not open, we recommend that you ask Cadence technical support or take a look at the gerber file.
