TI中文支持网Part Number:ADS54J66
Hi,
I am using ADS54j66 ADC on my board, and I have met some questions.
1. I want to use DDC mode 8, my sysref clk is 25MHz and sampling clk (clk input at CLKINP/M) is 250MSPS, is the Serdes line rate is just 5Gbps (10Gbps at 500MSPS)?
2. After the initial configuration as follows, I found the registers in page 6141 and page 6900 haven't been set (When I read these registers, they are all 00h). After I reconfigured these registers, I read their values. The registers in page 6141 are the values I set, but the registers in page 6900 are always 00h. I don't know if I have correctly configured these registers.
//Reset
24'h0000_81;
24'h4004_68;
24'h4003_00;
24'h60F7_01;
24'h60F7_00;
24'h70F7_01;
24'h70F7_00;
//Analog
24'h0011_80;
24'h0039_C0;
24'h0053_80;
24'h0059_20;
//IL Reset
24'h6000_01;
24'h6000_00;
24'h7000_01;
24'h7000_00;
//DECIMATION FILTER PAGE
24'h4003_41;
24'h4004_61;
24'h6000_08; //mode 8
24'h7000_08;
24'h6001_04; //always write 1
24'h7001_04;
//JESD ANALOG PAGE
24'h4003_00;
24'h4004_6A;
24'h6017_40; //PLL reset
24'h6017_00;
24'h7017_40;
24'h7017_00;
24'h6016_02; //JESD PLL mode 40x
24'h7016_02;
//JESD DIGITAL PAGE
24'h4003_00;
24'h4004_69;
24'h6000_C0;
24'h7000_C0;
24'h6001_01; //JESD mode 20x
24'h7001_01;
24'h6006_09; //k = 10
24'h7006_09;
24'h6005_80; //scramble enabled
24'h7005_80;
Amy Luo：
您好，
感谢您对TI产品的关注！由于问题比较复杂，已将您的问题发布在E2E英文技术论坛上，由资深的英文论坛工程师为您提供帮助。 您也可以点击下帖链接了解进展：
https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1317489/ads54j66-some-problems-about-spi-configuration
,
Amy Luo：
I was looking into this issue and there is an example on page 46 of the data sheet that says that register 6000h needs to be written 40h to enable JESD mode overwrite. Can you please try this after switching to the digital JESD page and let me know the results?
