TI中文支持网问题背景描述如下：
cmpss3的输入信号为正弦波，设定高阈值与低阈值，一个周期之内，在高阈值以上PWM开波，低阈值以下PWM关波。我们使用CMPSS3、X-bar、Trip4、Trip5、DCAEVT2、DCBEVT2来配置。
问题描述如下：
cmpss3的CtripH和CtripL信号通过如下配置能不能分别传递Trip4和Trip5，再由Trip4和Trip5分别控制DCAEVT2和DCBEVT2，在一个周期内实现需求。
相关代码配置如下：
EALLOW;
//Configure DCA to be TRIP5
EPwmxRegs->TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;//011: DCAL = HI, DCAH = don't care
EPwmxRegs->DCTRIPSEL.bit.DCAHCOMPSEL = 0xf; //Configure Trip5 to be DCAHCOMPSEL EPwmxRegs->DCAHTRIPSEL.bit.TRIPINPUT5 = 1;
//Configure DCB to be TRIP4
EPwmxRegs->TZDCSEL.bit.DCBEVT2 = TZ_DCBH_HI;//100: DCBL = high, DCBH = don't care
EPwmxRegs->DCTRIPSEL.bit.DCBHCOMPSEL = 0011; //Configure Trip4 to be DCBHCOMPSEL
EPwmxRegs->DCBHTRIPSEL.bit.TRIPINPUT4 = 1; //Trip Input 4 selected as combinational ORed input to DCBL mux Reset type: SYSRSn
//Configure EVT2 DCA/DCB as CBC
EPwmxRegs->TZSEL.bit.DCAEVT2 = 1;//Enable DCAEVT2 as a CBC trip source for this ePWM module Reset type: SYSRSn
EPwmxRegs->TZSEL.bit.DCBEVT2 = 1;//Enable DCBEVT2 as a CBC trip source for this ePWM module Reset type: SYSRSn
//Configure DCA/DCB path to be unfiltered & async
EPwmxRegs->DCACTL.bit.EVT2SRCSEL = DC_EVT2;//Source Is DCBEVT2 Signal
EPwmxRegs->DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; //DCAEVT2 Force Synchronization Signal Select
EPwmxRegs->DCBCTL.bit.EVT2SRCSEL = DC_EVT2; //Source Is DCBEVT2 Signal
EPwmxRegs->DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; //DCBEVT2 Force Synchronization Signal Select*/
EDIS;
实验结果现在是，如果DCTRIPSEL.bit.DCAHCOMPSEL这个寄存器配置成0100（即选定TRIP5）,那么将得不到理论的效果，只有将其配置成0xf,才有需求的效果，但同时，DCBEVT也会触发，导致EPWMB动作，这种耦合一直存在。
如何将这两个TRIP和DCAEVT、DCBEVT分别对应起来呢？
盼望恢复，谢谢。
