SRC4382: Why is the DIT output frequency fixed at 44.1KHz?

Hi all,

I had a problem configuring DIT with SRC4382 and it never worked.

First application: I2S->PortA-> (optional SRC)->DIT
Second application: DIR->SRC->PortA

I'm now debugging the first application, where the digital audio source frequency is 1KHz sine wave:

1、I2S BCK=3.072MHz；
2、I2S LRCK = 48KHz；
3、I2S MCK = 6.144MHz；

Program Configuration:

0x03 = 0x01;
0x01 = 0x37;

The DIT output AESOUT was connected to the VM700T test, and the result was 44.1KHz, and the sine wave frequency was 918.8KHz. The sensation is directly divided by a 1.0884 multiplier value, and the calculation shows that 1.0884 = 48KHz/44.1KHz.

I thought there was a problem with the signal source, I used the FPGA to pass this signal source directly to the DIT4192 chip, and then through the DIT4192 output access to the VM700T test, the result is 48KHz sampling, the sine wave frequency is 1KHz, completely normal.

I tried PortA->SRC->DIT->VM700T and the result was still 44.1KHz@918.8KHz.

No workaround has been found at the moment, it can be determined that there is no problem with the signal source,

How do I configure SRC4382?

Thank you.

Cherry Zhou：

Hi,

We're looking into this issue and please expect the response by next business day.

Thanks

,

chen wang：

Thanks Cherry.

,

Cherry Zhou：

Hello Chen,

I assume you have  monitored the output of SRC and you see it is giving 44.1K not 48K.

There are bits that need to be set in some registers such as :

Register 07: Transmitter Control Register 1  bits    TXDIV[1:0] that  are used to select the Transmitter master clock divider, which determines the output frame rate. Check that register to be sure.

The 2 registers you mentioned looked ok ( you set it to be 24B I2S) however when I look at the clocks you provided above  and using the equation of  Bclk=2xword length x fs, then  word length= 3.072M/ (2*48k)= 32bit. The SRC supports input and output sampling rates up to 216kHz, with audio data word lengths up to 24 bits. 

So for 24bit , 2 channels and 48k clock, the bit clock should be 2x24x48k=2,304,000   ( so something to check)

I am also  attaching a couple of  sample files  that you can use as starting point and modify them as you need.

# sample I2C script
# set interface mode to i2c fast
i i2cfast
# set register page to 0
w e0 7f 00
# dir setup is default with audio muted for loss of lock condition and rxcko enabled
w e0 0d 00
w e0 0e 09
# pll1 setup for 24.576mhz rxcki p is 2 j is 8 d is 0
w e0 0f 22
w e0 10 00
w e0 11 00
# set gpo1 for dir nonaudio flag
w e0 1b 06
# set gpo2 for dir nonvalid flag
w e0 1c 07# set gpo3 for dir emphasis flag
w e0 1d 05
# set gpo4 for dir parity error flag
w e0 1e 0d
# src setup is default with the dir as the input data source
# mclk is the ref clock source
w e0 2d 02
w e0 2e 00
w e0 2f 00
w e0 30 00
w e0 31 00
# dit setup with the src as the input data source and mclk as master clock
# mclk divider is 512 to set the output frame rate
# block start is an output and valid audio is indicated
# c and u data is sourced from the data buffers in register page 2
w e0 07 7c
w e0 08 00
w e0 09 01
# power up all blocks except port a and b
w e0 01 27
# disable dit buffer transfers
w e0 08 08
# set register page to 2
w e0 7f 02
# set dit channel status data for bytes 0 thru 2
# professional use pcm audio no emphasis locked 48khz sampling freq# all other channel status bytes are set to default 0x00 value
w e0 00 81
w e0 01 81
w e0 02 10
w e0 03 10
w e0 04 34
w e0 05 34
# set register page to 0
w e0 7f 00
# enable dit buffer transfers
w e0 08 00
b
# dit setup for 96k output
w e0 07 3c
w e0 08 08
w e0 7f 02
w e0 00 80
w e0 01 80
w e0 08 08
w e0 09 08
w e0 7f 00
w e0 08 00
b
# dit setup for 192k
w e0 07 1c
w e0 08 08
w e0 7f 02
w e0 00 80
w e0 01 80
w e0 08 18
w e0 09 18
w e0 7f 00
w e0 08 00

# sample I2C script
# set interface mode to i2c fast
i i2cfast
# set register page to 0
w e0 7f 00
# port a setup as slave with i2s data format
w e0 03 01
w e0 04 00
# dit setup with port a as the data source
# mclk is selected as the master clock and divided by 512 to set the output frame rate
# block start is an output and valid audio data is indicated by the v bit
# the v bit source is the valid bit in control register 0x07
# c and u data are sourced from the data buffers on register page 2
w e0 07 64
w e0 08 00
w e0 09 01
# dir setup with rxcki as the ref clock and rx1 as the input
# rxcko output is enabled with no clock divider
# audio output data is muted for loss of lock condition
# recovered clock is stopped for loss of lock conditionw e0 0d 00
w e0 0e 09
# pll1 setup for 24.576mhz rxcki where p is 2 j is 8 d is 0
w e0 0f 22
w e0 10 00
w e0 11 00
# port b setup as master with the dir output and rxcko as the data and master clock source
# data format is i2s and the rxcko is divided by 512
w e0 05 29
w e0 06 0b
# set gpo1 to dir block start clock outputw e0 1b 0a
# set gpo2 to dir sync clock output
w e0 1c 0e
# set gpo3 to dir channel status data serial output
w e0 1d 08
# set gpo3 to dir user data serial output
w e0 1e 09
# power up all blocks except the src
w e0 01 3e
# disable dit c and u buffer transfers
w e0 08 08
# set register page to 2
w e0 7f 02
# set dit channel status data for bytes 0 thru 2
# professional mode with pcm audio no emphasis locked 48khz sampling freq# all other channel status bytes are set to default 0x00 value
w e0 00 81
w e0 01 81
w e0 02 10
w e0 03 10
w e0 04 34
w e0 05 34
# set register page to 0
w e0 7f 00
# enable dit c and u buffer transfers
w e0 08 00
b
# dit and port b setup for 96k input and output
w e0 06 09
w e0 07 24
w e0 08 08
w e0 7f 02
w e0 00 80
w e0 01 80
w e0 08 08
w e0 09 08
w e0 7f 00
w e0 08 00
b
# dit and port b setup for 192k input and output
w e0 06 08
w e0 07 04
w e0 08 08
w e0 7f 02
w e0 00 80
w e0 01 80
w e0 08 18
w e0 09 18
w e0 7f 00
w e0 08 00

I hope these can help you to set it up correctly. Let me know if you need more help.

Thanks