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使用280049 CMPSS实现电流 CBC功能

2019-09-17 分类：C2000™ 32位实时 MCU 阅读(684)

大家好，使用280049 CMPSS实现电流CBC功能遇到问题：现象1 ：同样代码在TI LAUNCHXL-F280049C开发板模拟触发和恢复PWM1和2 CBC功能发波关波正常，在控制板上波一直发不出来？？现象2：带仿真器+LAUNCHXL板查看EPwm1Regs.TZCBCFLG.DCAEVT2 =1和DCBEVT2=1为什么还能发出波来？控制板同样有DCAEVT2=1 DCBEVT2=1没波发出，配置如下，请分析指导，急件，谢谢。

// ILA—>A5—>CMP2HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL = 3;
// ILB—>A10–>CMP7HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP7HPMXSEL = 0;

// I115–>B3—>CMP3HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP3HPMXSEL = 3;

// NEG signal comes from DAC Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss7Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;

// Configure CTRIPOUT path Cmpss2Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH; 

Cmpss7Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss2Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS

Cmpss2Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;

Cmpss2Regs.DACHVALS.bit.DACVAL = 3050;// IA:0—>1 trip

Cmpss7Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss7Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss7Regs.DACHVALS.bit.DACVAL = 3050; // IB:0—>1 trip

Cmpss3Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss3Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss3Regs.DACHVALS.bit.DACVAL = (Uint16)CUR115_CBC_CMPS_BUCK; // I115:1—>0 trip

// ILA—>CMPSS2.CTRIPH—>TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 1; EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP4–>DCAH
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN4; // DCAH = Comp2H

// TRIP7–>DCBH
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care // for buck ILA: 0—>1 ok
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;

// DCBH–>DCBEVT2
EPwm1Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care // for buck I115: 1—>0 ok
EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC; EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm1Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC

EPwm1Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm1Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm1Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

// ILB—>CMPSS7.CTRIPH—>TRIP5
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX12 = 1; EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX12 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP5–>DCAH
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN5; // DCAH = Comp7H
// TRIP5–>DCAL
//EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TRIPIN5; // DCAL = Comp7H
// TRIP7–>DCBH
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care for buck ILB: 0—>1 ok EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path

// DCBH–>DCBEVT2
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care for buck I115: 1—>0 ok
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm2Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC
EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm2Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm2Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

Green Deng：请问你提到的“控制板”是你自己设计制作的板子还是TI的套件？看了一下你的问题更偏向硬件问题？上述的程序是参考的TI例程还是自己编写的？

大家好，使用280049 CMPSS实现电流CBC功能遇到问题：现象1 ：同样代码在TI LAUNCHXL-F280049C开发板模拟触发和恢复PWM1和2 CBC功能发波关波正常，在控制板上波一直发不出来？？现象2：带仿真器+LAUNCHXL板查看EPwm1Regs.TZCBCFLG.DCAEVT2 =1和DCBEVT2=1为什么还能发出波来？控制板同样有DCAEVT2=1 DCBEVT2=1没波发出，配置如下，请分析指导，急件，谢谢。

// ILA—>A5—>CMP2HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL = 3;
// ILB—>A10–>CMP7HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP7HPMXSEL = 0;

// I115–>B3—>CMP3HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP3HPMXSEL = 3;

// NEG signal comes from DAC Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss7Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;

// Configure CTRIPOUT path Cmpss2Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH; 

Cmpss7Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss2Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS

Cmpss2Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;

Cmpss2Regs.DACHVALS.bit.DACVAL = 3050;// IA:0—>1 trip

Cmpss7Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss7Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss7Regs.DACHVALS.bit.DACVAL = 3050; // IB:0—>1 trip

Cmpss3Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss3Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss3Regs.DACHVALS.bit.DACVAL = (Uint16)CUR115_CBC_CMPS_BUCK; // I115:1—>0 trip

// ILA—>CMPSS2.CTRIPH—>TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 1; EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP4–>DCAH
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN4; // DCAH = Comp2H

// TRIP7–>DCBH
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care // for buck ILA: 0—>1 ok
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;

// DCBH–>DCBEVT2
EPwm1Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care // for buck I115: 1—>0 ok
EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC; EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm1Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC

EPwm1Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm1Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm1Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

// ILB—>CMPSS7.CTRIPH—>TRIP5
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX12 = 1; EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX12 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP5–>DCAH
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN5; // DCAH = Comp7H
// TRIP5–>DCAL
//EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TRIPIN5; // DCAL = Comp7H
// TRIP7–>DCBH
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care for buck ILB: 0—>1 ok EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path

// DCBH–>DCBEVT2
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care for buck I115: 1—>0 ok
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm2Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC
EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm2Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm2Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

user1431255：

回复 Green Deng:

您好，

控制板是我们制作的，不打开CBC相关功能，采样发波等都正常，参考28035自己编写的，因为280049例程没看到有cmpss,Xbar,TZDC, CBC,您有例程提供吗？

在开发板上仿真看到EPwm1Regs.TZFLG中的DCAEVT2=1和DCBEVT2=1对应PWM为什么还能发出波？？

大家好，使用280049 CMPSS实现电流CBC功能遇到问题：现象1 ：同样代码在TI LAUNCHXL-F280049C开发板模拟触发和恢复PWM1和2 CBC功能发波关波正常，在控制板上波一直发不出来？？现象2：带仿真器+LAUNCHXL板查看EPwm1Regs.TZCBCFLG.DCAEVT2 =1和DCBEVT2=1为什么还能发出波来？控制板同样有DCAEVT2=1 DCBEVT2=1没波发出，配置如下，请分析指导，急件，谢谢。

// ILA—>A5—>CMP2HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL = 3;
// ILB—>A10–>CMP7HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP7HPMXSEL = 0;

// I115–>B3—>CMP3HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP3HPMXSEL = 3;

// NEG signal comes from DAC Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss7Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;

// Configure CTRIPOUT path Cmpss2Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH; 

Cmpss7Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss2Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS

Cmpss2Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;

Cmpss2Regs.DACHVALS.bit.DACVAL = 3050;// IA:0—>1 trip

Cmpss7Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss7Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss7Regs.DACHVALS.bit.DACVAL = 3050; // IB:0—>1 trip

Cmpss3Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss3Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss3Regs.DACHVALS.bit.DACVAL = (Uint16)CUR115_CBC_CMPS_BUCK; // I115:1—>0 trip

// ILA—>CMPSS2.CTRIPH—>TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 1; EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP4–>DCAH
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN4; // DCAH = Comp2H

// TRIP7–>DCBH
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care // for buck ILA: 0—>1 ok
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;

// DCBH–>DCBEVT2
EPwm1Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care // for buck I115: 1—>0 ok
EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC; EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm1Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC

EPwm1Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm1Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm1Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

// ILB—>CMPSS7.CTRIPH—>TRIP5
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX12 = 1; EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX12 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP5–>DCAH
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN5; // DCAH = Comp7H
// TRIP5–>DCAL
//EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TRIPIN5; // DCAL = Comp7H
// TRIP7–>DCBH
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care for buck ILB: 0—>1 ok EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path

// DCBH–>DCBEVT2
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care for buck I115: 1—>0 ok
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm2Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC
EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm2Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm2Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

Green Deng：

回复 user1431255:

个人认为，官方板子上使用正常而自己板子出现问题的话会不会是硬件问题更大些？特别是涉及到TZ模块，如果硬件上出现错误导致波形无法产生的可能性更大。
例程的问题我帮你咨询一下美国工程师看是否能提供。

大家好，使用280049 CMPSS实现电流CBC功能遇到问题：现象1 ：同样代码在TI LAUNCHXL-F280049C开发板模拟触发和恢复PWM1和2 CBC功能发波关波正常，在控制板上波一直发不出来？？现象2：带仿真器+LAUNCHXL板查看EPwm1Regs.TZCBCFLG.DCAEVT2 =1和DCBEVT2=1为什么还能发出波来？控制板同样有DCAEVT2=1 DCBEVT2=1没波发出，配置如下，请分析指导，急件，谢谢。

// ILA—>A5—>CMP2HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL = 3;
// ILB—>A10–>CMP7HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP7HPMXSEL = 0;

// I115–>B3—>CMP3HP
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP3HPMXSEL = 3;

// NEG signal comes from DAC Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
Cmpss7Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;

// Configure CTRIPOUT path Cmpss2Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH; 

Cmpss7Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;

Cmpss2Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS

Cmpss2Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;

Cmpss2Regs.DACHVALS.bit.DACVAL = 3050;// IA:0—>1 trip

Cmpss7Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss7Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss7Regs.DACHVALS.bit.DACVAL = 3050; // IB:0—>1 trip

Cmpss3Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
Cmpss3Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss3Regs.DACHVALS.bit.DACVAL = (Uint16)CUR115_CBC_CMPS_BUCK; // I115:1—>0 trip

// ILA—>CMPSS2.CTRIPH—>TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 1; EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP4–>DCAH
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN4; // DCAH = Comp2H

// TRIP7–>DCBH
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care // for buck ILA: 0—>1 ok
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;

// DCBH–>DCBEVT2
EPwm1Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care // for buck I115: 1—>0 ok
EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC; EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm1Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC

EPwm1Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm1Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm1Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

// ILB—>CMPSS7.CTRIPH—>TRIP5
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX12 = 1; EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX12 = 1;

// I115–>CMPSS3.CTRIPH—>TRIP7
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 1; EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;
// TRIP5–>DCAH
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN5; // DCAH = Comp7H
// TRIP5–>DCAL
//EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TRIPIN5; // DCAL = Comp7H
// TRIP7–>DCBH
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN7; // DCBH = Comp3H

// DCAH–>DCAEVT2
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAH = high, DCAL = don't care for buck ILB: 0—>1 ok EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path

// DCBH–>DCBEVT2
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_LOW; // DCAH = high, DCAL = don't care for buck I115: 1—>0 ok
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 CBC
EPwm2Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 CBC
EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; EPwm2Regs.TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
EPwm2Regs.TZCLR.bit.CBCPULSE = 0; // CNT=0 Pulse clrar CBC

Green Deng：

回复 Green Deng:

目前官方还没有F280049的例程，可以参考F28377D的，PWM模块非常相似，也包含CBC：
dev.ti.com/…/node

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