SK-AM64B: A53核在CCS上跑hello world 裸机，下载代码报错

下面是进入调试界面，点链接A53内核后，GEL的初始化过程和后面加载代码的报错信息

CS_DAP_0: GEL Output: Configuring ATCM for the R5Fs
CS_DAP_0: GEL Output: ATCM Configured.
CS_DAP_0: GEL Output: R5F Halt bits set.
CS_DAP_0: GEL Output: Configuring bootvectors
CS_DAP_0: GEL Output: Bootvectors configured.
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Debugging enabled
CS_DAP_0: GEL Output: Programming all PLLs.
CS_DAP_0: GEL Output: Programming Main PLL 0 (Main PLL)
CS_DAP_0: GEL Output: Unlocked PLL MMRs.
CS_DAP_0: GEL Output: Read configuration MMRs.
CS_DAP_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
CS_DAP_0: GEL Output: HSDIV presence value = 0x000003FF
CS_DAP_0: GEL Output: Number of hsidvs: 10
CS_DAP_0: GEL Output: Parsed PLL configuration information.
CS_DAP_0: GEL Output: Note: deskew PLL programming isn't implemented yet
CS_DAP_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
CS_DAP_0: GEL Output: For debugging:CS_DAP_0: GEL Output: Base address: 0x680000
CS_DAP_0: GEL Output: PLL index: 0x00000000
CS_DAP_0: GEL Output: PLL index register base: 0x00000000
CS_DAP_0: GEL Output: Register: 0x00000020
CS_DAP_0: GEL Output: Clocking scheme: 1
CS_DAP_0: GEL Output: Set PLL to external bypass via Control MMR.
CS_DAP_0: GEL Output: Disabled PLL
CS_DAP_0: GEL Output: Enabled noise-cancelling DAC.
CS_DAP_0: GEL Output: Enabled the Delta-Sigma modulator.
CS_DAP_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
CS_DAP_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
CS_DAP_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
CS_DAP_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
CS_DAP_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
CS_DAP_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
CS_DAP_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
CS_DAP_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
CS_DAP_0: GEL Output: Programming HSDIV #0
CS_DAP_0: GEL Output: hsdiv_value: 3
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #0 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #1
CS_DAP_0: GEL Output: hsdiv_value: 9
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #1 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #2
CS_DAP_0: GEL Output: hsdiv_value: 24
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #2 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #3
CS_DAP_0: GEL Output: hsdiv_value: 14
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #3 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #4
CS_DAP_0: GEL Output: hsdiv_value: 7
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #4 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #5
CS_DAP_0: GEL Output: hsdiv_value: 4
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #5 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #6
CS_DAP_0: GEL Output: hsdiv_value: 3
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #6 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #7
CS_DAP_0: GEL Output: hsdiv_value: 3
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #7 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #8
CS_DAP_0: GEL Output: hsdiv_value: 7
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #8 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #9
CS_DAP_0: GEL Output: hsdiv_value: 2
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #9 programmed.
CS_DAP_0: GEL Output: Selected Main Domain PLL Controller.
CS_DAP_0: GEL Output: Cleared bit 0 in the PLL controller control register.
CS_DAP_0: GEL Output: Cleared bit 5 in the PLL Controller control register.
CS_DAP_0: GEL Output: PLL controller is now in bypass mode.
CS_DAP_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller.
CS_DAP_0: GEL Output: Set PLLDIV1 (output_div1).
CS_DAP_0: GEL Output: addr: 0x00410124 = 0x00008000
CS_DAP_0: GEL Output: Clear GOSET.
CS_DAP_0: GEL Output: GOSTAT is clear.
CS_DAP_0: GEL Output: Set PLLDIV1 (output_div1).
CS_DAP_0: GEL Output: Set ALN1.
CS_DAP_0: GEL Output: addr: 0x00410104 = 0x00000012
CS_DAP_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller.
CS_DAP_0: GEL Output: addr: 0x00410148 = 0x00000002
CS_DAP_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1).
CS_DAP_0: GEL Output: Set GOSET to 1.
CS_DAP_0: GEL Output: GOSTAT is clear.
CS_DAP_0: GEL Output: Enable PLL Controller (write to bit 0 in control register).
CS_DAP_0: GEL Output: Set GOSET to 0.
CS_DAP_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free.
CS_DAP_0: GEL Output: Set the enable bit in the control register.
CS_DAP_0: GEL Output: PLL is locked.
CS_DAP_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
CS_DAP_0: GEL Output: Main PLL 0 (Main PLL) Set.
CS_DAP_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
CS_DAP_0: GEL Output: Unlocked PLL MMRs.
CS_DAP_0: GEL Output: Read configuration MMRs.
CS_DAP_0: GEL Output: temp value (HSDIV_Presence) = 0x0000007F
CS_DAP_0: GEL Output: HSDIV presence value = 0x0000007F
CS_DAP_0: GEL Output: Number of hsidvs: 7
CS_DAP_0: GEL Output: Parsed PLL configuration information.
CS_DAP_0: GEL Output: Note: deskew PLL programming isn't implemented yet
CS_DAP_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
CS_DAP_0: GEL Output: For debugging:CS_DAP_0: GEL Output: Base address: 0x680000
CS_DAP_0: GEL Output: PLL index: 0x00000001
CS_DAP_0: GEL Output: PLL index register base: 0x00001000
CS_DAP_0: GEL Output: Register: 0x00000020
CS_DAP_0: GEL Output: Clocking scheme: 1
CS_DAP_0: GEL Output: Set PLL to external bypass via Control MMR.
CS_DAP_0: GEL Output: Disabled PLL
CS_DAP_0: GEL Output: Enabled noise-cancelling DAC.
CS_DAP_0: GEL Output: Enabled the Delta-Sigma modulator.
CS_DAP_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
CS_DAP_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
CS_DAP_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
CS_DAP_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
CS_DAP_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
CS_DAP_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
CS_DAP_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
CS_DAP_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
CS_DAP_0: GEL Output: Programming HSDIV #0
CS_DAP_0: GEL Output: hsdiv_value: 9
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #0 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #1
CS_DAP_0: GEL Output: hsdiv_value: 11
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #1 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #2
CS_DAP_0: GEL Output: hsdiv_value: 4
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #2 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #3
CS_DAP_0: GEL Output: hsdiv_value: 9
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #3 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #4
CS_DAP_0: GEL Output: hsdiv_value: 79
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #4 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #5
CS_DAP_0: GEL Output: hsdiv_value: 5
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #5 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #6
CS_DAP_0: GEL Output: hsdiv_value: 15
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #6 programmed.
CS_DAP_0: GEL Output: Set the enable bit in the control register.
CS_DAP_0: GEL Output: PLL is locked.
CS_DAP_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
CS_DAP_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
CS_DAP_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
CS_DAP_0: GEL Output: Unlocked PLL MMRs.
CS_DAP_0: GEL Output: Read configuration MMRs.
CS_DAP_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
CS_DAP_0: GEL Output: HSDIV presence value = 0x000003FF
CS_DAP_0: GEL Output: Number of hsidvs: 10
CS_DAP_0: GEL Output: Parsed PLL configuration information.
CS_DAP_0: GEL Output: Note: deskew PLL programming isn't implemented yet
CS_DAP_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
CS_DAP_0: GEL Output: For debugging:CS_DAP_0: GEL Output: Base address: 0x680000
CS_DAP_0: GEL Output: PLL index: 0x00000002
CS_DAP_0: GEL Output: PLL index register base: 0x00002000
CS_DAP_0: GEL Output: Register: 0x00000020
CS_DAP_0: GEL Output: Clocking scheme: 1
CS_DAP_0: GEL Output: Set PLL to external bypass via Control MMR.
CS_DAP_0: GEL Output: Disabled PLL
CS_DAP_0: GEL Output: Enabled noise-cancelling DAC.
CS_DAP_0: GEL Output: Enabled the Delta-Sigma modulator.
CS_DAP_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
CS_DAP_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
CS_DAP_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
CS_DAP_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
CS_DAP_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
CS_DAP_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
CS_DAP_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
CS_DAP_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
CS_DAP_0: GEL Output: Programming HSDIV #0
CS_DAP_0: GEL Output: hsdiv_value: 5
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #0 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #1
CS_DAP_0: GEL Output: i: 1, HSDIV value is -1, don't program this one
CS_DAP_0: GEL Output: HSDIV clock output disabled.
CS_DAP_0: GEL Output: HSDIV #1 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #2
CS_DAP_0: GEL Output: hsdiv_value: 8
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #2 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #3
CS_DAP_0: GEL Output: hsdiv_value: 5
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #3 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #4
CS_DAP_0: GEL Output: hsdiv_value: 17
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #4 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #5
CS_DAP_0: GEL Output: hsdiv_value: 7
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #5 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #6
CS_DAP_0: GEL Output: hsdiv_value: 7
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #6 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #7
CS_DAP_0: GEL Output: hsdiv_value: 17
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #7 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #8
CS_DAP_0: GEL Output: i: 8, HSDIV value is -1, don't program this one
CS_DAP_0: GEL Output: HSDIV clock output disabled.
CS_DAP_0: GEL Output: HSDIV #8 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #9
CS_DAP_0: GEL Output: hsdiv_value: 4
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #9 programmed.
CS_DAP_0: GEL Output: Set the enable bit in the control register.
CS_DAP_0: GEL Output: PLL is locked.
CS_DAP_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
CS_DAP_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
CS_DAP_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
CS_DAP_0: GEL Output: Unlocked PLL MMRs.
CS_DAP_0: GEL Output: Read configuration MMRs.
CS_DAP_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001
CS_DAP_0: GEL Output: HSDIV presence value = 0x00000001
CS_DAP_0: GEL Output: Number of hsidvs: 1
CS_DAP_0: GEL Output: Parsed PLL configuration information.
CS_DAP_0: GEL Output: Note: deskew PLL programming isn't implemented yet
CS_DAP_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
CS_DAP_0: GEL Output: For debugging:CS_DAP_0: GEL Output: Base address: 0x680000
CS_DAP_0: GEL Output: PLL index: 0x00000008
CS_DAP_0: GEL Output: PLL index register base: 0x00008000
CS_DAP_0: GEL Output: Register: 0x00000020
CS_DAP_0: GEL Output: Clocking scheme: 1
CS_DAP_0: GEL Output: Set PLL to external bypass via Control MMR.
CS_DAP_0: GEL Output: Disabled PLL
CS_DAP_0: GEL Output: Enabled noise-cancelling DAC.
CS_DAP_0: GEL Output: Enabled the Delta-Sigma modulator.
CS_DAP_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
CS_DAP_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
CS_DAP_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
CS_DAP_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
CS_DAP_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
CS_DAP_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
CS_DAP_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
CS_DAP_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
CS_DAP_0: GEL Output: Programming HSDIV #0
CS_DAP_0: GEL Output: hsdiv_value: 1
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #0 programmed.
CS_DAP_0: GEL Output: Set the enable bit in the control register.
CS_DAP_0: GEL Output: PLL is locked.
CS_DAP_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
CS_DAP_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
CS_DAP_0: GEL Output: Programming Main PLL 12 (DDR PLL)
CS_DAP_0: GEL Output: Unlocked PLL MMRs.
CS_DAP_0: GEL Output: Read configuration MMRs.
CS_DAP_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001
CS_DAP_0: GEL Output: HSDIV presence value = 0x00000001
CS_DAP_0: GEL Output: Number of hsidvs: 1
CS_DAP_0: GEL Output: Parsed PLL configuration information.
CS_DAP_0: GEL Output: Note: deskew PLL programming isn't implemented yet
CS_DAP_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
CS_DAP_0: GEL Output: For debugging:CS_DAP_0: GEL Output: Base address: 0x680000
CS_DAP_0: GEL Output: PLL index: 0x0000000C
CS_DAP_0: GEL Output: PLL index register base: 0x0000C000
CS_DAP_0: GEL Output: Register: 0x00000020
CS_DAP_0: GEL Output: Clocking scheme: 1
CS_DAP_0: GEL Output: Set PLL to external bypass via Control MMR.
CS_DAP_0: GEL Output: Disabled PLL
CS_DAP_0: GEL Output: Enabled noise-cancelling DAC.
CS_DAP_0: GEL Output: Enabled the Delta-Sigma modulator.
CS_DAP_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
CS_DAP_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
CS_DAP_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
CS_DAP_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
CS_DAP_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
CS_DAP_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
CS_DAP_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
CS_DAP_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
CS_DAP_0: GEL Output: Programming HSDIV #0
CS_DAP_0: GEL Output: hsdiv_value: 3
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #0 programmed.
CS_DAP_0: GEL Output: Set the enable bit in the control register.
CS_DAP_0: GEL Output: PLL is locked.
CS_DAP_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
CS_DAP_0: GEL Output: Main PLL 12 (DDR PLL) Set.
CS_DAP_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
CS_DAP_0: GEL Output: Unlocked PLL MMRs.
CS_DAP_0: GEL Output: Read configuration MMRs.
CS_DAP_0: GEL Output: temp value (HSDIV_Presence) = 0x00000003
CS_DAP_0: GEL Output: HSDIV presence value = 0x00000003
CS_DAP_0: GEL Output: Number of hsidvs: 2
CS_DAP_0: GEL Output: Parsed PLL configuration information.
CS_DAP_0: GEL Output: Note: deskew PLL programming isn't implemented yet
CS_DAP_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
CS_DAP_0: GEL Output: For debugging:CS_DAP_0: GEL Output: Base address: 0x680000
CS_DAP_0: GEL Output: PLL index: 0x0000000E
CS_DAP_0: GEL Output: PLL index register base: 0x0000E000
CS_DAP_0: GEL Output: Register: 0x00000020
CS_DAP_0: GEL Output: Clocking scheme: 1
CS_DAP_0: GEL Output: Set PLL to external bypass via Control MMR.
CS_DAP_0: GEL Output: Disabled PLL
CS_DAP_0: GEL Output: Enabled noise-cancelling DAC.
CS_DAP_0: GEL Output: Enabled the Delta-Sigma modulator.
CS_DAP_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
CS_DAP_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
CS_DAP_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
CS_DAP_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
CS_DAP_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
CS_DAP_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
CS_DAP_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
CS_DAP_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
CS_DAP_0: GEL Output: Programming HSDIV #0
CS_DAP_0: GEL Output: hsdiv_value: 2
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #0 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #1
CS_DAP_0: GEL Output: hsdiv_value: 2
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #1 programmed.
CS_DAP_0: GEL Output: Set the enable bit in the control register.
CS_DAP_0: GEL Output: PLL is locked.
CS_DAP_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
CS_DAP_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
CS_DAP_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
CS_DAP_0: GEL Output: Unlocked PLL MMRs.
CS_DAP_0: GEL Output: Read configuration MMRs.
CS_DAP_0: GEL Output: temp value (HSDIV_Presence) = 0x0000001F
CS_DAP_0: GEL Output: HSDIV presence value = 0x0000001F
CS_DAP_0: GEL Output: Number of hsidvs: 5
CS_DAP_0: GEL Output: Parsed PLL configuration information.
CS_DAP_0: GEL Output: Note: deskew PLL programming isn't implemented yet
CS_DAP_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
CS_DAP_0: GEL Output: For debugging:CS_DAP_0: GEL Output: Base address: 0x04040000
CS_DAP_0: GEL Output: PLL index: 0x00000000
CS_DAP_0: GEL Output: PLL index register base: 0x00000000
CS_DAP_0: GEL Output: Register: 0x00000020
CS_DAP_0: GEL Output: Clocking scheme: 1
CS_DAP_0: GEL Output: Set PLL to external bypass via Control MMR.
CS_DAP_0: GEL Output: Disabled PLL
CS_DAP_0: GEL Output: Enabled noise-cancelling DAC.
CS_DAP_0: GEL Output: Enabled the Delta-Sigma modulator.
CS_DAP_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
CS_DAP_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
CS_DAP_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
CS_DAP_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
CS_DAP_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
CS_DAP_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
CS_DAP_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
CS_DAP_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
CS_DAP_0: GEL Output: Programming HSDIV #0
CS_DAP_0: GEL Output: hsdiv_value: 5
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #0 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #1
CS_DAP_0: GEL Output: hsdiv_value: 24
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #1 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #2
CS_DAP_0: GEL Output: hsdiv_value: 24
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #2 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #3
CS_DAP_0: GEL Output: hsdiv_value: 11
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #3 programmed.
CS_DAP_0: GEL Output: Programming HSDIV #4
CS_DAP_0: GEL Output: hsdiv_value: 11
CS_DAP_0: GEL Output: HSDIV reset asserted
CS_DAP_0: GEL Output: HSDIV divider value programmed.
CS_DAP_0: GEL Output: HSDIV reset de-asserted
CS_DAP_0: GEL Output: HSDIV #4 programmed.
CS_DAP_0: GEL Output: Selected MCU Domain PLL Conntroller.
CS_DAP_0: GEL Output: Cleared bit 0 in the PLL controller control register.
CS_DAP_0: GEL Output: Cleared bit 5 in the PLL Controller control register.
CS_DAP_0: GEL Output: PLL controller is now in bypass mode.
CS_DAP_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller.
CS_DAP_0: GEL Output: Set PLLDIV1 (output_div1).
CS_DAP_0: GEL Output: addr: 0x04020124 = 0x00008000
CS_DAP_0: GEL Output: Clear GOSET.
CS_DAP_0: GEL Output: GOSTAT is clear.
CS_DAP_0: GEL Output: Set PLLDIV1 (output_div1).
CS_DAP_0: GEL Output: Set ALN1.
CS_DAP_0: GEL Output: addr: 0x04020104 = 0x00000012
CS_DAP_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller.
CS_DAP_0: GEL Output: addr: 0x04020148 = 0x00000002
CS_DAP_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1).
CS_DAP_0: GEL Output: Set GOSET to 1.
CS_DAP_0: GEL Output: GOSTAT is clear.
CS_DAP_0: GEL Output: Enable PLL Controller (write to bit 0 in control register).
CS_DAP_0: GEL Output: Set GOSET to 0.
CS_DAP_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free.
CS_DAP_0: GEL Output: Set the enable bit in the control register.
CS_DAP_0: GEL Output: PLL is locked.
CS_DAP_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
CS_DAP_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
CS_DAP_0: GEL Output: All PLLs programmed.
CS_DAP_0: GEL Output: Powering up all PSC power domains in progress…
CS_DAP_0: GEL Output: Powering up MAIN domain peripherals…
CS_DAP_0: GEL Output: Powering up GP_CORE_CTL.CS_DAP_0: GEL Output: Powering up LPSC_DMSC
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_MAIN_TEST
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_MAIN_PBIST
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_EMMC_4B
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_EMMC_8B
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_USB
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_ADC
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_DEBUGSS
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_GPMC
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_EMIF_CFG
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_EMIF_DATA
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_MCAN_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_MCAN_1
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_SA2UL
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_SERDES_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_PCIE_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up GP_CORE_CTL done.CS_DAP_0: GEL Output: Powering up PD_A53_CLUSTER_0.CS_DAP_0: GEL Output: Powering up LPSC_A53_CLUSTER_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_A53_CLUSTER_0_PBIST
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_A53_CLUSTER_0 done.CS_DAP_0: GEL Output: Powering up PD_A53_0.CS_DAP_0: GEL Output: Powering up LPSC_A53_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_A53_0 done.CS_DAP_0: GEL Output: Powering up PD_A53_1.CS_DAP_0: GEL Output: Powering up LPSC_A53_1
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_A53_1 done.CS_DAP_0: GEL Output: Powering up PD_PULSAR_0.CS_DAP_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_PULSAR_0 done.CS_DAP_0: GEL Output: Powering up PD_PULSAR_1.CS_DAP_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_PULSAR_1 done.CS_DAP_0: GEL Output: Powering up PD_ICSSG_0.CS_DAP_0: GEL Output: Powering up LPSC_ICSSG_0
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_ICSSG_0 done.CS_DAP_0: GEL Output: Powering up PD_ICSSG_1.CS_DAP_0: GEL Output: Powering up LPSC_ICSSG_1
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_ICSSG_1 done.CS_DAP_0: GEL Output: Powering up PD_CPSW.CS_DAP_0: GEL Output: Powering up LPSC_CPSW3G
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_CPSW done.CS_DAP_0: GEL Output: Powering up all MAIN domain peripherals done.CS_DAP_0: GEL Output: Powering up MCU Domain peripherals.CS_DAP_0: GEL Output: Powering up GP_CORE_CTL_MCU.CS_DAP_0: GEL Output: Powering up LPSC_TEST
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_MAIN2MCU
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up LPSC_MCU2MAIN
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: No change needed.
CS_DAP_0: GEL Output: Powering up GP_CORE_CTL_MCU done.CS_DAP_0: GEL Output: Powering up PD_M4F.CS_DAP_0: GEL Output: Powering up LPSC_M4F
CS_DAP_0: GEL Output: Running from R5 or A53
CS_DAP_0: GEL Output: Power domain and module state changed successfully.
CS_DAP_0: GEL Output: Powering up PD_M4F done.CS_DAP_0: GEL Output: Powering up MCU Domain peripherals done.CS_DAP_0: GEL Output: Powering up all PSC power domains done!
CS_DAP_0: GEL Output:CS_DAP_0: GEL Output: *****DDR is configured using R5 or A53 GELs
CortexA53_0: GEL Output: Device Type is GP
CortexA53_0: GEL Output: Running from R5 or A53
CortexA53_0: GEL Output: Device Type is GP
CortexA53_0: GEL Output: Running from R5 or A53
CortexA53_0: GEL Output: —>>> LPDDR4 Initialization is in progress … <<<—
CortexA53_0: GEL Output: —>>> ECC Disabled <<<—
CortexA53_0: GEL Output: —>>> DDR controller programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> DDR controller programming completed… <<<—
CortexA53_0: GEL Output: —>>> DDR PI programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> DDR PI programming completed… <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Data Slice 0 programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Data Slice 0 programming completed… <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Data Slice 1 programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Data Slice 1 programming completed… <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Address Slice 0 programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Data Slice 2 programming completed… <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Address Slice 1 programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Address Slice 1 programming completed… <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Address slice 2 programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> DDR PHY Address Slice 2 programming completed… <<<—
CortexA53_0: GEL Output: —>>> DDR PHY programming in progress.. <<<—
CortexA53_0: GEL Output: —>>> Set PHY registers for all FSPs simultaneously (multicast)… <<<—
CortexA53_0: GEL Output: —>>> DDR PHY programming completed… <<<—
CortexA53_0: GEL Output: Running from R5 or A53
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_25MHz
CortexA53_0: GEL Output: hsdiv_value: 63
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: —>>> Set DDR PLL to 25MHz for FSP F0… <<<—
CortexA53_0: GEL Output: Triggering start bit from PI…
CortexA53_0: GEL Output: —>>> DDR PI initialization started… <<<—
CortexA53_0: GEL Output: Triggering start bit from CTL…
CortexA53_0: GEL Output: —>>> DDR CTL initialization started… <<<—
CortexA53_0: GEL Output: —>>> Inside DDR_Change_freq_ack function … <<<—
CortexA53_0: GEL Output: —>>> Waiting for first frequency change request … <<<—
CortexA53_0: GEL Output: Iter 1: Frequency change request type 2 received from controllerCortexA53_0: GEL Output: Running from R5 or A53
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
CortexA53_0: GEL Output: hsdiv_value: 3
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: Iter 2: Frequency change request type 0 received from controllerCortexA53_0: GEL Output: Running from R5 or A53
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_25MHz
CortexA53_0: GEL Output: hsdiv_value: 63
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: Iter 3: Frequency change request type 2 received from controllerCortexA53_0: GEL Output: Running from R5 or A53
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
CortexA53_0: GEL Output: hsdiv_value: 3
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: —>>> Frequency Change request handshake is completed… <<<—
CortexA53_0: GEL Output: Polling PI DONE bit…
CortexA53_0: GEL Output: pi_int_status = 0x27C0A001…
CortexA53_0: GEL Output: – PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
CortexA53_0: GEL Output: – PI_LVL_DONE_BIT set: The leveling operation has completed.
CortexA53_0: GEL Output: – PI_TDFI_INIT_TIME_OUT_BIT set: The tDFI init complete timed out.
CortexA53_0: GEL Output: – PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
CortexA53_0: GEL Output: – PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
CortexA53_0: GEL Output: – PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
CortexA53_0: GEL Output: – PI_CALVL_DONE_BIT set: A CA training operation has been completed.
CortexA53_0: GEL Output: – PI_WDQLVL_DONE_BIT set: A write DQ training operation has been completed.
CortexA53_0: GEL Output: – Not documented bit set.
CortexA53_0: GEL Output: ctl_int_status = 0x02000000…
CortexA53_0: GEL Output: —>>> DDR Initialization completed… <<<—
CortexA53_0: GEL Output: —>>> LPDDR4 Initialization is DONE! <<<—
CortexA53_0: File Loader: Verification failed: Values at address 0x0000000000004A31 do not match Please verify target memory and memory map.
CortexA53_0: GEL: File: D:\ti\workspace_v9\AM6442\AM6442_TEST\Debug\AM6442_TEST.out: a data verification error occurred, file load failed.

麻烦TI的工程师帮我看看问题出在哪里的。从GEL加载过程的打印信息来看，芯片初始化应该是没啥问题的吧。

Shine：

请问其他核可以连接吗？是否按照下面的文档操作的？https://dev.ti.com/tirex/explore/node?a=VLyFKFf__4.12.1&node=A__AD2nw6Uu4txAz2eqZdShBg__com.ti.MCU_PLUS_SDK_AM64X__rN4Qml4__LATEST

,

user18914063：

其它所有核都是差不多一样结果，文件加载失败

,

Shine：

请问是否按照下面的文档操作的？https://dev.ti.com/tirex/explore/node?a=VLyFKFf__4.12.1&node=A__AD2nw6Uu4txAz2eqZdShBg__com.ti.MCU_PLUS_SDK_AM64X__rN4Qml4__LATEST

,

user18914063：

我没有用文档里的步骤，刚看了下你给的这个文档链接，貌似也没看到有建立hell worle裸机工程的介绍，我是直接在CCS里面，按照一般建立hello world 裸机工程的步骤建立的工程，然后在工程中对目标进行配置

在这个页面下，对每个目标逐个添加对应的GEL文件。

另外，我在如下目录中找到了SDK带的裸机hello worle工程，导入后，编译报错

报错信息如下：

我现在有如下几个疑问：

一 建立hello world裸机工程，应该不需要做什么复杂的配置啥的吧，最多就是在目标配置能力给每个核添加正确的GEL文件就可以跑了呀

二 SDK里面的这个hello world裸机工程的报错，是怎么回事呢，是有什么地方操作没对吗

,

Shine：

建议先按照上面SDK文档里的步骤操作一下，请看下面红色框内的步骤。