TMS320DM8148: TI814x-DDR3-Init-U-Boot for MT41K128M16JT-125 IT K

Hi ,

Basing on ti-ezsdk_dm814x-evm_5_05_02_00, my custome board repalced the DDR3 as 4 pcs of MT41K128M16JT-125 IT K.

I am trying to following such likes. but most disappearred or cannot be downloaded.

https://rashkash103.github.io/ti-wiki/processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot.html

https://www.ti2k.com/wp-content/uploads/ti2k/DeyiSupport_DSP_adding-ddr3-changes-to-am33xx-soc-using-mt41k128m16jt-125-k-part-number

https://rashkash103.github.io/ti-wiki/processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling.html

https://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide

Would you provide the the full files and step to let me try to generate the DDR relavent parameters for ddr_defs_ti814x.h like below

/* TI814X DDR2 PHY CFG parameters <emif0 : emif1> */
#define DDR2_PHY_RD_DQS_CS0_DEFINE ((emif == 0) ? 0x35 : 0x35)
#define DDR2_PHY_WR_DQS_CS0_DEFINE ((emif == 0) ? 0x20 : 0x20)
#define DDR2_PHY_RD_DQS_GATE_CS0_DEFINE ((emif == 0) ? 0x90 : 0x90)
#define DDR2_PHY_WR_DATA_CS0_DEFINE ((emif == 0) ? 0x50 : 0x50)
#define DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE 0x80

/* TI814X DDR3 PHY CFG parameters <emif0 : emif 1> */
#define DDR3_PHY_RD_DQS_CS0_BYTE0 ((emif == 0) ? 0x37 : 0x3A)
#define DDR3_PHY_RD_DQS_CS0_BYTE1 ((emif == 0) ? 0x37 : 0x3C)
#define DDR3_PHY_RD_DQS_CS0_BYTE2 ((emif == 0) ? 0x33 : 0x38)
#define DDR3_PHY_RD_DQS_CS0_BYTE3 ((emif == 0) ? 0x33 : 0x34)

#define DDR3_PHY_WR_DQS_CS0_BYTE0 ((emif == 0) ? 0x41 : 0x48)
#define DDR3_PHY_WR_DQS_CS0_BYTE1 ((emif == 0) ? 0x48 : 0x4D)
#define DDR3_PHY_WR_DQS_CS0_BYTE2 ((emif == 0) ? 0x50 : 0x54)
#define DDR3_PHY_WR_DQS_CS0_BYTE3 ((emif == 0) ? 0x4F : 0x51)

#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE0 ((emif == 0) ? 0xEA : 0xE1)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE1 ((emif == 0) ? 0x119 : 0x103)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE2 ((emif == 0) ? 0x11F : 0x120)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE3 ((emif == 0) ? 0x14F : 0x149)

#define DDR3_PHY_WR_DATA_CS0_BYTE0 ((emif == 0) ? 0x8A : 0x8F)
#define DDR3_PHY_WR_DATA_CS0_BYTE1 ((emif == 0) ? 0x87 : 0x87)
#define DDR3_PHY_WR_DATA_CS0_BYTE2 ((emif == 0) ? 0x87 : 0x83)
#define DDR3_PHY_WR_DATA_CS0_BYTE3 ((emif == 0) ? 0x7F : 0x84)

/* TI814X DDR3 EMIF CFG Registers values 533MHz */
#define DDR3_EMIF_READ_LATENCY 0x0017020B
#define DDR3_EMIF_TIM1 0x0EEF3723
#define DDR3_EMIF_TIM2 0x30AA7FE2
#define DDR3_EMIF_TIM3 0x50FFE56F
#define DDR3_EMIF_REF_CTRL 0x0000103D
#define DDR3_EMIF_SDRAM_CONFIG 0x61C122B2
#define DDR3_EMIF_SDRAM_ZQCR 0x50074BE1

Best Regards,

Bobby

Refgards,

Bobby

Gary Lu：

Hello, I have consulted e2e engineer, it will take some time, thank you!