TDA4VH-Q1: tda4vh-配置sgmii&serdes

tda4vh sdk8.6平台中

rtos中调试2-0的sgmii phy

需要配置sgmii与serdes

serdes1 lane 1

serdes 2 lane 0 1 2 3 4 

过程中出现pll错误

CpswMacPort_setSgmiiInterface: MAC 4: SERDES PLL is not locked

[MCU2_0]17.794998 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]17.810964 s: PHY 0 is no alive
[MCU2_0]17.811022 s: PHY 1 is no alive
[MCU2_0]17.811053 s: PHY 2 is alive
[MCU2_0]17.811080 s: PHY 3 is no alive
[MCU2_0]17.811107 s: PHY 4 is no alive
[MCU2_0]17.811135 s: PHY 5 is no alive
[MCU2_0]17.811161 s: PHY 6 is no alive
[MCU2_0]17.811187 s: PHY 7 is no alive
[MCU2_0]17.811214 s: PHY 8 is no alive
[MCU2_0]17.811241 s: PHY 9 is no alive
[MCU2_0]17.811267 s: PHY 10 is no alive
[MCU2_0]17.811295 s: PHY 11 is no alive
[MCU2_0]17.811323 s: PHY 12 is no alive
[MCU2_0]17.811350 s: PHY 13 is no alive
[MCU2_0]17.811377 s: PHY 14 is no alive
[MCU2_0]17.811404 s: PHY 15 is no alive
[MCU2_0]17.811432 s: PHY 16 is no alive
[MCU2_0]17.811459 s: PHY 17 is no alive
[MCU2_0]17.811486 s: PHY 18 is no alive
[MCU2_0]17.811513 s: PHY 19 is no alive
[MCU2_0]17.811547 s: PHY 20 is no alive
[MCU2_0]17.811575 s: PHY 21 is no alive
[MCU2_0]17.811601 s: PHY 22 is no alive
[MCU2_0]17.811627 s: PHY 23 is no alive
[MCU2_0]17.811654 s: PHY 24 is no alive
[MCU2_0]17.811681 s: PHY 25 is no alive
[MCU2_0]17.811707 s: PHY 26 is no alive
[MCU2_0]17.811734 s: PHY 27 is no alive
[MCU2_0]17.811760 s: PHY 28 is no alive
[MCU2_0]17.811787 s: PHY 29 is no alive
[MCU2_0]17.811813 s: PHY 30 is no alive
[MCU2_0]17.811846 s: EnetMcm_enablePorts() +to open MAC port: 3
[MCU2_0]17.812042 s: CpswMacPort_setSgmiiInterface: MAC 4: SERDES PLL is not locked 0x0
[MCU2_0]17.812078 s: CpswMacPort_setSgmiiInterface: 
[MCU2_0]17.812113 s: Assertion @ Line: 2201 in src/mod/cpsw_macport.c: false

{/* Configure SerDes clocks */EthFwBoard_configTorrentClks();/* Configure SerDes for QSGMII functionality */boardStatus = Board_serdesCfgSgmii();EnetAppUtils_assert(boardStatus == BOARD_SOK);boardStatus = Board_serdesCfgSgmii_serdes1();// EnetAppUtils_assert(boardStatus == BOARD_SOK);

Board_STATUS Board_CfgSgmii_serdes1(void)
{CSL_SerdesResult result;CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;CSL_SerdesLaneEnableParams serdesLane0EnableParams  = {0};
	printf("%s %d \n",__func__,__LINE__);memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));/* SGMII Config */serdesLane0EnableParams.serdesInstance= (CSL_SerdesInstance)CSL_TORRENT_SERDES1;serdesLane0EnableParams.baseAddr= CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;serdesLane0EnableParams.refClock= CSL_SERDES_REF_CLOCK_100M;serdesLane0EnableParams.refClkSrc= CSL_SERDES_REF_CLOCK_INT1;serdesLane0EnableParams.linkRate= CSL_SERDES_LINK_RATE_1p25G;serdesLane0EnableParams.numLanes= 0x2;serdesLane0EnableParams.laneMask= 0x4;serdesLane0EnableParams.SSC_mode= CSL_SERDES_NO_SSC;serdesLane0EnableParams.phyType= CSL_SERDES_PHY_TYPE_SGMII;serdesLane0EnableParams.operatingMode= CSL_SERDES_FUNCTIONAL_MODE;serdesLane0EnableParams.phyInstanceNum= BOARD_SERDES_LANE_SELECT_CPSW;serdesLane0EnableParams.pcieGenType= CSL_SERDES_PCIE_GEN3;serdesLane0EnableParams.laneCtrlRate[0]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[0]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[1]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[1]= CSL_SERDES_LOOPBACK_DISABLED;CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,1U);result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.baseAddr,serdesLane0EnableParams.refClock,serdesLane0EnableParams.refClkSrc,serdesLane0EnableParams.serdesInstance,serdesLane0EnableParams.phyType);if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}/* Assert PHY reset and disable all lanes */CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);/* Load the Serdes Config File */result = CSL_serdesEthernetInit(&serdesLane0EnableParams);/* Return error if input params are invalid */if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}/* Common Lane Enable API for lane enable, pll enable etc */laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);if (laneRetVal != 0){return BOARD_FAIL;}return BOARD_SOK;
}

从打印看,好像2-0卡死了

Board_ethConfigCpsw9g 663
[MCU2_0]61.678121 s: Board_CfgSgmii_serdes1 393 
[MCU2_1]47.263577 s: CIO: Init ... Done !!!
[MCU2_1]47.263628 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]47.263661 s: CPU is running FreeRTOS
[MCU2_1]47.263681 s: APP: Init ... !!!
[MCU2_1]47.263700 s: SCICLIENT: Init ... !!!
[MCU2_1]47.263865 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]47.263899 s: SCICLIENT: DMSC FW revision 0x8  

请问一下,如何配置原理图中所需要的sgmii 及serdes并确保及正常工作

Cherry Zhou：

您好，您的问题我们需要升级到英文论坛看下，链接如下：

e2e.ti.com/…/tda4vh-q1-configure-sgmii-serdes

,

yk z：

对于serdes 1 tx1/rx1 (lane1)这边修改了如下没有卡住，但显示pll没locked住

ti-processor-sdk-rtos-j784s4-evm-08_06_00_14\ethfw\utils\board\src\j784s4\board_j784s4_evm.c

 if (gEthFwBoard.serdesAllowed){+Sciclient_pmSetModuleState(TISCI_DEV_SERDES_10G1,+TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,+TISCI_MSG_FLAG_AOP,+SCICLIENT_SERVICE_WAIT_FOREVER);/* Configure SerDes clocks */-// EthFwBoard_configTorrentClks();+EthFwBoard_configTorrentClks1();/* Configure SerDes for QSGMII functionality */// boardStatus = Board_serdesCfgSgmii();// EnetAppUtils_assert(boardStatus == BOARD_SOK);+boardStatus = Board_serdesCfgSgmii_serdes1();EnetAppUtils_assert(boardStatus == BOARD_SOK);

static void EthFwBoard_configTorrentClks1(void)
{uint32_t moduleId;uint32_t clkId;uint32_t clkRateHz;moduleId= TISCI_DEV_SERDES_10G1;clkId= TISCI_DEV_SERDES_10G1_CORE_REF_CLK;clkRateHz = 100000000U;EnetAppUtils_clkRateSet(moduleId, clkId, clkRateHz);EnetAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);
}

Board_STATUS Board_serdesCfgSgmii_serdes1(void)
{CSL_SerdesResult result;CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;CSL_SerdesLaneEnableParams serdesLane0EnableParams= {0};printf("%s %d \n",__func__,__LINE__);memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));/* SGMII Config */serdesLane0EnableParams.serdesInstance= (CSL_SerdesInstance)CSL_TORRENT_SERDES1;serdesLane0EnableParams.baseAddr= CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;serdesLane0EnableParams.refClock= CSL_SERDES_REF_CLOCK_100M;serdesLane0EnableParams.refClkSrc= CSL_SERDES_REF_CLOCK_INT0;serdesLane0EnableParams.linkRate= CSL_SERDES_LINK_RATE_1p25G;serdesLane0EnableParams.numLanes= 0x2;serdesLane0EnableParams.laneMask= 0x3;serdesLane0EnableParams.SSC_mode= CSL_SERDES_NO_SSC;serdesLane0EnableParams.phyType= CSL_SERDES_PHY_TYPE_SGMII;serdesLane0EnableParams.operatingMode= CSL_SERDES_FUNCTIONAL_MODE;serdesLane0EnableParams.phyInstanceNum= BOARD_SERDES_LANE_SELECT_CPSW;serdesLane0EnableParams.pcieGenType= CSL_SERDES_PCIE_GEN3;serdesLane0EnableParams.laneCtrlRate[0]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[0]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[1]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[1]= CSL_SERDES_LOOPBACK_DISABLED;printf("%s %d \n",__func__,__LINE__);CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);printf("%s %d \n",__func__,__LINE__);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,0U);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,1U);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,2U);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,3U);printf("%s %d \n",__func__,__LINE__);result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.baseAddr,serdesLane0EnableParams.refClock,serdesLane0EnableParams.refClkSrc,serdesLane0EnableParams.serdesInstance,serdesLane0EnableParams.phyType);printf("%s %d \n",__func__,__LINE__);if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}printf("%s %d \n",__func__,__LINE__);/* Assert PHY reset and disable all lanes */CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);printf("%s %d \n",__func__,__LINE__);/* Load the Serdes Config File */result = CSL_serdesEthernetInit(&serdesLane0EnableParams);/* Return error if input params are invalid */if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}printf("%s %d \n",__func__,__LINE__);/* Common Lane Enable API for lane enable, pll enable etc */laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);if (laneRetVal != 0){return BOARD_FAIL;}printf("%s %d \n",__func__,__LINE__);return BOARD_SOK;
}

日志显示

[MCU2_0]15.998196 s: PHY 29 is no alive
[MCU2_0]15.998221 s: PHY 30 is no alive
[MCU2_0]15.998250 s: EnetMcm_enablePorts() +to open MAC port: 3
[MCU2_0]15.998441 s: status reg:0x0
[MCU2_0]15.998482 s: CpswMacPort_setSgmiiInterface: MAC 4: SERDES PLL is not locked 0x0
[MCU2_0]15.998519 s: CpswMacPort_setSgmiiInterface:[MCU2_0]15.998553 s: Assertion @ Line: 2201 in src/mod/cpsw_macport.c: false
[MCU2_1]2.475382 s: CIO: Init ... Done !!!
[MCU2_1]2.475433 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]2.475464 s: CPU is running FreeRTOS

/opt/vision_apps/vision_apps_init.sh
root@j784s4-evm:~# [MCU2_0]2.480101 s: CIO: Init ... Done !!!
[MCU2_0]2.480141 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]2.480171 s: CPU is running FreeRTOS
[MCU2_0]2.480191 s: APP: Init ... !!!
[MCU2_0]2.480211 s: SCICLIENT: Init ... !!!
[MCU2_0]2.480361 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_0]2.480395 s: SCICLIENT: DMSC FW revision 0x8[MCU2_0]2.480423 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]2.480453 s: SCICLIENT: Init ... Done !!!
[MCU2_0]2.480475 s: UDMA: Init ... !!!
[MCU2_0]2.481455 s: UDMA: Init ... Done !!!
[MCU2_0]2.481492 s: UDMA: Init ... !!!
[MCU2_0]2.482020 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0]2.482071 s: MEM: Init ... !!!
[MCU2_0]2.482105 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e2000000 of size 16777216 bytes !!!
[MCU2_0]2.482164 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
[MCU2_0]2.482216 s: MEM: Init ... Done !!!
[MCU2_0]2.482238 s: IPC: Init ... !!!
[MCU2_0]2.482286 s: IPC: 11 CPUs participating in IPC !!!
[MCU2_0]2.482328 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]15.768644 s: IPC: HLOS is ready !!!
[MCU2_0]15.790634 s: IPC: Init ... Done !!!
[MCU2_0]15.790681 s: APP: Syncing with 10 CPUs ... !!!
[MCU2_0]15.871887 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU2_0]15.871925 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]15.873711 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]15.873752 s: ETHFW: Init ... !!!
[MCU2_0]15.874989 s: zyk Board_init 204 cfg 0x10000000
[MCU2_0]15.875035 s: zyk Board_ethConfigCpsw9g 653
[MCU2_0]15.875070 s: zyk Board_ethConfigCpsw9g 663
[MCU2_0]15.980117 s: zyk EthFwBoard_configQenet 433
[MCU2_0]15.980155 s: zyk EthFwBoard_configQenet 440
[MCU2_0]15.980190 s: Board_CfgSgmii_serdes1 393[MCU2_0]15.980226 s: Board_CfgSgmii_serdes1 415[MCU2_0]15.980274 s: Board_CfgSgmii_serdes1 418[MCU2_0]15.980311 s: Board_CfgSgmii_serdes1 445[MCU2_0]15.980363 s: Board_CfgSgmii_serdes1 453[MCU2_0]15.980396 s: Board_CfgSgmii_serdes1 459[MCU2_0]15.980431 s: Board_CfgSgmii_serdes1 463[MCU2_0]15.980532 s: Board_CfgSgmii_serdes1 472[MCU2_0]15.980565 s: CSL_serdesLaneEnable 880[MCU2_0]15.980597 s: CSL_serdesLaneEnable 893[MCU2_0]15.980630 s: CSL_serdesLaneEnable 903[MCU2_0]15.980662 s: CSL_serdesLaneEnable 903[MCU2_0]15.980694 s: CSL_serdesLaneEnable 911[MCU2_0]15.980725 s: CSL_serdesLaneEnable 932[MCU2_0]15.980764 s: CSL_serdesLaneEnable 942[MCU2_0]15.980797 s: CSL_serdesLaneEnable 949[MCU2_0]15.980830 s: CSL_serdesLaneEnable 962[MCU2_0]15.980863 s: CSL_serdesLaneEnable 962[MCU2_0]15.980895 s: CSL_serdesLaneEnable 962[MCU2_0]15.980927 s: CSL_serdesLaneEnable 962[MCU2_0]15.980964 s: CSL_serdesLaneEnable 962[MCU2_0]15.980996 s: CSL_serdesLaneEnable 969[MCU2_0]15.981028 s: CSL_serdesLaneEnable 973[MCU2_0]15.981059 s: Board_CfgSgmii_serdes1 480[MCU2_0]15.981093 s: zyk EthFwBoard_configQenet 442
[MCU2_0]15.981126 s: zyk EthFwBoard_configQenet 446
[MCU2_0]15.981342 s: Warning: Using 6 MAC address(es) from static pool
[MCU2_0]15.981410 s: ETHFW: Shared multicasts (software fanout):
[MCU2_0]15.981441 s: ETHFW: Reserved multicasts:
[MCU2_0]15.981463 s:01:80:c2:00:00:0e
[MCU2_0]15.981507 s:01:1b:19:00:00:00
[MCU2_0]15.981703 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]15.997431 s: PHY 0 is no alive
[MCU2_0]15.997488 s: PHY 1 is no alive
[MCU2_0]15.997515 s: PHY 2 is alive
[MCU2_0]15.997540 s: PHY 3 is no alive
[MCU2_0]15.997565 s: PHY 4 is no alive
[MCU2_0]15.997590 s: PHY 5 is no alive
[MCU2_0]15.997615 s: PHY 6 is no alive
[MCU2_0]15.997639 s: PHY 7 is no alive
[MCU2_0]15.997664 s: PHY 8 is no alive
[MCU2_0]15.997689 s: PHY 9 is no alive
[MCU2_0]15.997713 s: PHY 10 is no alive
[MCU2_0]15.997739 s: PHY 11 is no alive
[MCU2_0]15.997763 s: PHY 12 is no alive
[MCU2_0]15.997789 s: PHY 13 is no alive
[MCU2_0]15.997813 s: PHY 14 is no alive
[MCU2_0]15.997838 s: PHY 15 is no alive
[MCU2_0]15.997863 s: PHY 16 is no alive
[MCU2_0]15.997889 s: PHY 17 is no alive
[MCU2_0]15.997913 s: PHY 18 is no alive
[MCU2_0]15.997938 s: PHY 19 is no alive
[MCU2_0]15.997971 s: PHY 20 is no alive
[MCU2_0]15.997996 s: PHY 21 is no alive
[MCU2_0]15.998021 s: PHY 22 is no alive
[MCU2_0]15.998046 s: PHY 23 is no alive
[MCU2_0]15.998071 s: PHY 24 is no alive
[MCU2_0]15.998096 s: PHY 25 is no alive
[MCU2_0]15.998121 s: PHY 26 is no alive
[MCU2_0]15.998146 s: PHY 27 is no alive
[MCU2_0]15.998171 s: PHY 28 is no alive
[MCU2_0]15.998196 s: PHY 29 is no alive
[MCU2_0]15.998221 s: PHY 30 is no alive
[MCU2_0]15.998250 s: EnetMcm_enablePorts() +to open MAC port: 3
[MCU2_0]15.998441 s: status reg:0x0
[MCU2_0]15.998482 s: CpswMacPort_setSgmiiInterface: MAC 4: SERDES PLL is not locked 0x0
[MCU2_0]15.998519 s: CpswMacPort_setSgmiiInterface:[MCU2_0]15.998553 s: Assertion @ Line: 2201 in src/mod/cpsw_macport.c: false
[MCU2_1]2.475382 s: CIO: Init ... Done !!!
[MCU2_1]2.475433 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]2.475464 s: CPU is running FreeRTOS
[MCU2_1]2.475485 s: APP: Init ... !!!
[MCU2_1]2.475503 s: SCICLIENT: Init ... !!!
[MCU2_1]2.475707 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]2.475741 s: SCICLIENT: DMSC FW revision 0x8[MCU2_1]2.475768 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]2.475799 s: SCICLIENT: Init ... Done !!!
[MCU2_1]2.475822 s: UDMA: Init ... !!!
[MCU2_1]2.477327 s: UDMA: Init ... Done !!!
[MCU2_1]2.477376 s: MEM: Init ... !!!
[MCU2_1]2.477410 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e3000000 of size 16777216 bytes !!!
[MCU2_1]2.477469 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 60040000 of size 262144 bytes !!!
[MCU2_1]2.477520 s: MEM: Init ... Done !!!
[MCU2_1]2.477541 s: IPC: Init ... !!!
[MCU2_1]2.477587 s: IPC: 11 CPUs participating in IPC !!!
[MCU2_1]2.477627 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]15.771723 s: IPC: HLOS is ready !!!
[MCU2_1]15.793843 s: IPC: Init ... Done !!!
[MCU2_1]15.793888 s: APP: Syncing with 10 CPUs ... !!!
[MCU2_1]15.871886 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU2_1]15.871923 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]15.873746 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]15.873787 s: FVID2: Init ... !!!
[MCU2_1]15.873842 s: FVID2: Init ... Done !!!
[MCU2_1]15.873868 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]15.873891 s: SCICLIENT: Sciclient_pmSetModuleState module=92 state=2
[MCU2_1]15.874261 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]15.874291 s: SCICLIENT: Sciclient_pmSetModuleState module=96 state=2
[MCU2_1]15.874651 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]15.874677 s: VHWA: DOF Init ... !!!
[MCU2_1]15.880256 s: VHWA: DOF Init ... Done !!!
[MCU2_1]15.880296 s: VHWA: SDE Init ... !!!
[MCU2_1]15.882115 s: VHWA: SDE Init ... Done !!!
[MCU2_1]15.882152 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]15.882189 s:VX_ZONE_INIT:Enabled
[MCU2_1]15.882215 s:VX_ZONE_ERROR:Enabled
[MCU2_1]15.882237 s:VX_ZONE_WARNING:Enabled
[MCU2_1]15.883630 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1[MCU2_1]15.883818 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE[MCU2_1]15.884006 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF[MCU2_1]15.884052 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]15.884081 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]15.884322 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]15.884358 s: APP: Init ... Done !!!
[MCU2_1]15.884382 s: APP: Run ... !!!
[MCU2_1]15.884402 s: IPC: Starting echo test ...
[MCU2_1]15.888896 s: APP: Run ... Done !!!
[MCU2_1]15.890080 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.][MCU2_1]15.890197 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.][MCU2_1]15.890306 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.][MCU2_1]15.890408 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.][MCU2_1]15.890508 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.][MCU2_1]15.890613 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.][MCU2_1]15.890714 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU2_1]15.931228 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_0]2.532391 s: CIO: Init ... Done !!!
[MCU3_0]2.532444 s: ### CPU Frequency = 1000000000 Hz
[MCU3_0]2.532474 s: CPU is running FreeRTOS
[MCU3_0]2.532495 s: APP: Init ... !!!
[MCU3_0]2.532514 s: SCICLIENT: Init ... !!!
[MCU3_0]2.532653 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_0]2.532688 s: SCICLIENT: DMSC FW revision 0x8[MCU3_0]2.532715 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_0]2.532746 s: SCICLIENT: Init ... Done !!!
[MCU3_0]2.532769 s: MEM: Init ... !!!
[MCU3_0]2.532801 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e4000000 of size 8388608 bytes !!!
[MCU3_0]2.532857 s: MEM: Init ... Done !!!
[MCU3_0]2.532878 s: IPC: Init ... !!!
[MCU3_0]2.532921 s: IPC: 11 CPUs participating in IPC !!!
[MCU3_0]2.532960 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_0]15.783017 s: IPC: HLOS is ready !!!
[MCU3_0]15.804645 s: IPC: Init ... Done !!!
[MCU3_0]15.804690 s: APP: Syncing with 10 CPUs ... !!!
[MCU3_0]15.871887 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU3_0]15.871924 s: REMOTE_SERVICE: Init ... !!!
[MCU3_0]15.873900 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_0]15.873951 s:VX_ZONE_INIT:Enabled
[MCU3_0]15.873976 s:VX_ZONE_ERROR:Enabled
[MCU3_0]15.873999 s:VX_ZONE_WARNING:Enabled
[MCU3_0]15.875380 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-0[MCU3_0]15.875430 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_0]15.875462 s: APP: OpenVX Target kernel init ... !!!
[MCU3_0]15.875489 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_0]15.875514 s: APP: Init ... Done !!!
[MCU3_0]15.875537 s: APP: Run ... !!!
[MCU3_0]15.875557 s: IPC: Starting echo test ...
[MCU3_0]15.880934 s: APP: Run ... Done !!!
[MCU3_0]15.882106 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.][MCU3_0]15.882231 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.][MCU3_0]15.882347 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.][MCU3_0]15.882529 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_0]15.882732 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_0]15.882854 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_0]15.889477 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_0]15.931187 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_1]2.591455 s: CIO: Init ... Done !!!
[MCU3_1]2.591505 s: ### CPU Frequency = 1000000000 Hz
[MCU3_1]2.591537 s: CPU is running FreeRTOS
[MCU3_1]2.591559 s: APP: Init ... !!!
[MCU3_1]2.591578 s: SCICLIENT: Init ... !!!
[MCU3_1]2.591719 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_1]2.591757 s: SCICLIENT: DMSC FW revision 0x8[MCU3_1]2.591784 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_1]2.591815 s: SCICLIENT: Init ... Done !!!
[MCU3_1]2.591838 s: MEM: Init ... !!!
[MCU3_1]2.591870 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e4800000 of size 8388608 bytes !!!
[MCU3_1]2.591926 s: MEM: Init ... Done !!!
[MCU3_1]2.591948 s: IPC: Init ... !!!
[MCU3_1]2.591991 s: IPC: 11 CPUs participating in IPC !!!
[MCU3_1]2.592028 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_1]15.784169 s: IPC: HLOS is ready !!!
[MCU3_1]15.805868 s: IPC: Init ... Done !!!
[MCU3_1]15.805913 s: APP: Syncing with 10 CPUs ... !!!
[MCU3_1]15.871886 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU3_1]15.871924 s: REMOTE_SERVICE: Init ... !!!
[MCU3_1]15.873918 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_1]15.873971 s:VX_ZONE_INIT:Enabled
[MCU3_1]15.873996 s:VX_ZONE_ERROR:Enabled
[MCU3_1]15.874020 s:VX_ZONE_WARNING:Enabled
[MCU3_1]15.875412 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-1[MCU3_1]15.875464 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_1]15.875495 s: APP: OpenVX Target kernel init ... !!!
[MCU3_1]15.875522 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_1]15.875548 s: APP: Init ... Done !!!
[MCU3_1]15.875571 s: APP: Run ... !!!
[MCU3_1]15.875592 s: IPC: Starting echo test ...
[MCU3_1]15.880985 s: APP: Run ... Done !!!
[MCU3_1]15.882169 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.][MCU3_1]15.882297 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.][MCU3_1]15.882408 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.][MCU3_1]15.882533 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_1]15.882659 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_1]15.882885 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_1]15.889489 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU3_1]15.931206 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU4_0]2.808971 s: CIO: Init ... Done !!!
[MCU4_0]2.809026 s: ### CPU Frequency = 1000000000 Hz
[MCU4_0]2.809058 s: CPU is running FreeRTOS
[MCU4_0]2.809079 s: APP: Init ... !!!
[MCU4_0]2.809098 s: SCICLIENT: Init ... !!!
[MCU4_0]2.809243 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU4_0]2.809277 s: SCICLIENT: DMSC FW revision 0x8[MCU4_0]2.809303 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU4_0]2.809334 s: SCICLIENT: Init ... Done !!!
[MCU4_0]2.809357 s: UDMA: Init ... !!!
[MCU4_0]2.810434 s: UDMA: Init ... Done !!!
[MCU4_0]2.810485 s: MEM: Init ... !!!
[MCU4_0]2.810521 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e5000000 of size 8388608 bytes !!!
[MCU4_0]2.810585 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ a8dc9000 of size 524288 bytes !!!
[MCU4_0]2.810636 s: MEM: Init ... Done !!!
[MCU4_0]2.810657 s: IPC: Init ... !!!
[MCU4_0]2.810707 s: IPC: 11 CPUs participating in IPC !!!
[MCU4_0]2.810745 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU4_0]15.788518 s: IPC: HLOS is ready !!!
[MCU4_0]15.809904 s: IPC: Init ... Done !!!
[MCU4_0]15.809951 s: APP: Syncing with 10 CPUs ... !!!
[MCU4_0]15.871888 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU4_0]15.871921 s: REMOTE_SERVICE: Init ... !!!
[MCU4_0]15.873811 s: REMOTE_SERVICE: Init ... Done !!!
[MCU4_0]15.873850 s: FVID2: Init ... !!!
[MCU4_0]15.873903 s: FVID2: Init ... Done !!!
[MCU4_0]15.873930 s: VHWA: VPAC Init ... !!!
[MCU4_0]15.873952 s: SCICLIENT: Sciclient_pmSetModuleState module=400 state=2
[MCU4_0]15.874374 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU4_0]15.874405 s: VHWA: LDC Init ... !!!
[MCU4_0]15.878417 s: VHWA: LDC Init ... Done !!!
[MCU4_0]15.878453 s: VHWA: MSC Init ... !!!
[MCU4_0]15.887438 s: VHWA: MSC Init ... Done !!!
[MCU4_0]15.887474 s: VHWA: NF Init ... !!!
[MCU4_0]15.888467 s: VHWA: NF Init ... Done !!!
[MCU4_0]15.888498 s: VHWA: VISS Init ... !!!
[MCU4_0]15.895741 s: VHWA: VISS Init ... Done !!!
[MCU4_0]15.895784 s: VHWA: VPAC Init ... Done !!!
[MCU4_0]15.895818 s:VX_ZONE_INIT:Enabled
[MCU4_0]15.895842 s:VX_ZONE_ERROR:Enabled
[MCU4_0]15.895863 s:VX_ZONE_WARNING:Enabled
[MCU4_0]15.897176 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU4-0[MCU4_0]15.897366 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_NF[MCU4_0]15.897535 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_LDC1[MCU4_0]15.897719 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_MSC1[MCU4_0]15.897897 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_MSC2[MCU4_0]15.898124 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_VISS1[MCU4_0]15.898169 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU4_0]15.898197 s: APP: OpenVX Target kernel init ... !!!
[MCU4_0]15.924266 s: APP: OpenVX Target kernel init ... Done !!!
[MCU4_0]15.924301 s: VISS REMOTE SERVICE: Init ... !!!
[MCU4_0]15.924355 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU4_0]15.924382 s: UDMA Copy: Init ... !!!
[MCU4_0]15.925418 s: UDMA Copy: Init ... Done !!!
[MCU4_0]15.925453 s: APP: Init ... Done !!!
[MCU4_0]15.925476 s: APP: Run ... !!!
[MCU4_0]15.925497 s: IPC: Starting echo test ...
[MCU4_0]15.930590 s: APP: Run ... Done !!!
[MCU4_0]15.931896 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[.] mcu3_0[P] mcu3_1[.] mcu4_0[s] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.][MCU4_0]15.932011 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[.] mcu4_0[s] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.][MCU4_0]15.932118 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.][MCU4_0]15.932222 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.][MCU4_0]15.932324 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.][MCU4_0]15.932426 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.][MCU4_0]15.932530 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.][MCU4_0]15.932642 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU4_1]2.829259 s: CIO: Init ... Done !!!
[MCU4_1]2.829313 s: ### CPU Frequency = 1000000000 Hz
[MCU4_1]2.829345 s: CPU is running FreeRTOS
[MCU4_1]2.829365 s: APP: Init ... !!!
[MCU4_1]2.829384 s: SCICLIENT: Init ... !!!
[MCU4_1]2.829534 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU4_1]2.829569 s: SCICLIENT: DMSC FW revision 0x8[MCU4_1]2.829596 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU4_1]2.829627 s: SCICLIENT: Init ... Done !!!
[MCU4_1]2.829650 s: MEM: Init ... !!!
[MCU4_1]2.829682 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e5800000 of size 8388608 bytes !!!
[MCU4_1]2.829738 s: MEM: Init ... Done !!!
[MCU4_1]2.829760 s: IPC: Init ... !!!
[MCU4_1]2.829805 s: IPC: 11 CPUs participating in IPC !!!
[MCU4_1]2.829844 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU4_1]15.850562 s: IPC: HLOS is ready !!!
[MCU4_1]15.871798 s: IPC: Init ... Done !!!
[MCU4_1]15.871839 s: APP: Syncing with 10 CPUs ... !!!
[MCU4_1]15.871888 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU4_1]15.871921 s: REMOTE_SERVICE: Init ... !!!
[MCU4_1]15.873993 s: REMOTE_SERVICE: Init ... Done !!!
[MCU4_1]15.874098 s:VX_ZONE_INIT:Enabled
[MCU4_1]15.874124 s:VX_ZONE_ERROR:Enabled
[MCU4_1]15.874148 s:VX_ZONE_WARNING:Enabled
[MCU4_1]15.875478 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU4-1[MCU4_1]15.875523 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU4_1]15.875553 s: APP: OpenVX Target kernel init ... !!!
[MCU4_1]15.875578 s: APP: OpenVX Target kernel init ... Done !!!
[MCU4_1]15.875605 s: APP: Init ... Done !!!
[MCU4_1]15.875628 s: APP: Run ... !!!
[MCU4_1]15.875649 s: IPC: Starting echo test ...
[MCU4_1]15.881033 s: APP: Run ... Done !!!
[MCU4_1]15.882168 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.][MCU4_1]15.882294 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.][MCU4_1]15.882407 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.][MCU4_1]15.882535 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU4_1]15.882725 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU4_1]15.882887 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU4_1]15.889514 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][MCU4_1]15.931220 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P][C7x_1 ]3.438854 s: CIO: Init ... Done !!!
[C7x_1 ]3.438868 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]3.438879 s: CPU is running FreeRTOS
[C7x_1 ]3.438887 s: APP: Init ... !!!
[C7x_1 ]3.438895 s: SCICLIENT: Init ... !!!
[C7x_1 ]3.439024 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]3.439037 s: SCICLIENT: DMSC FW revision 0x8[C7x_1 ]3.439048 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]3.439060 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]3.439068 s: UDMA: Init ... !!!
[C7x_1 ]3.440061 s: UDMA: Init ... Done !!!
[C7x_1 ]3.440072 s: MEM: Init ... !!!
[C7x_1 ]3.440083 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 108000000 of size 134217728 bytes !!!
[C7x_1 ]3.440103 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 68000000 of size 3145728 bytes !!!
[C7x_1 ]3.440122 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ]3.440139 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]3.440157 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 118000000 of size 134217728 bytes !!!
[C7x_1 ]3.440175 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000001) @ 100000000 of size 134217728 bytes !!!
[C7x_1 ]3.440194 s: MEM: Created heap (DDR_SCRATCH_NON_, id=6, flags=0x00000001) @ 110000000 of size 134217728 bytes !!!
[C7x_1 ]3.440213 s: MEM: Init ... Done !!!
[C7x_1 ]3.440221 s: IPC: Init ... !!!
[C7x_1 ]3.440233 s: IPC: 11 CPUs participating in IPC !!!
[C7x_1 ]3.440248 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]15.765997 s: IPC: HLOS is ready !!!
[C7x_1 ]15.770539 s: IPC: Init ... Done !!!
[C7x_1 ]15.770555 s: APP: Syncing with 10 CPUs ... !!!
[C7x_1 ]15.871889 s: APP: Syncing with 10 CPUs ... Done !!!
[C7x_1 ]15.871908 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]15.872086 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]15.872111 s:VX_ZONE_INIT:Enabled
[C7x_1 ]15.872123 s:VX_ZONE_ERROR:Enabled
[C7x_1 ]15.872133 s:VX_ZONE_WARNING:Enabled
[C7x_1 ]15.872499 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1[C7x_1 ]15.872588 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2[C7x_1 ]15.872695 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3[C7x_1 ]15.872802 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4[C7x_1 ]15.872860 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5[C7x_1 ]15.872918 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6[C7x_1 ]15.872975 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7[C7x_1 ]15.873034 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8[C7x_1 ]15.873059 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]15.873073 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]15.873654 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]15.873670 s: APP: Init ... Done !!!
[C7x_1 ]15.873680 s: APP: Run ... !!!
[C7x_1 ]15.873689 s: IPC: Starting echo test ...
[C7x_1 ]15.873947 s: APP: Run ... Done !!!
[C7x_1 ]15.876354 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[s] c7x_2[x] c7x_3[P] c7x_4[x][C7x_1 ]15.876707 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[s] c7x_2[x] c7x_3[P] c7x_4[P][C7x_1 ]15.877267 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P][C7x_1 ]15.881982 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P][C7x_1 ]15.882051 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P][C7x_1 ]15.882095 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P][C7x_1 ]15.889467 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P][C7x_1 ]15.931207 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P][C7x_2 ]4.083661 s: CIO: Init ... Done !!!
[C7x_2 ]4.083674 s: ### CPU Frequency = 1000000000 Hz
[C7x_2 ]4.083685 s: CPU is running FreeRTOS
[C7x_2 ]4.083694 s: APP: Init ... !!!
[C7x_2 ]4.083701 s: SCICLIENT: Init ... !!!
[C7x_2 ]4.083826 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_2 ]4.083840 s: SCICLIENT: DMSC FW revision 0x8[C7x_2 ]4.083851 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_2 ]4.083862 s: SCICLIENT: Init ... Done !!!
[C7x_2 ]4.083871 s: UDMA: Init ... !!!
[C7x_2 ]4.084820 s: UDMA: Init ... Done !!!
[C7x_2 ]4.084830 s: MEM: Init ... !!!
[C7x_2 ]4.084841 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 108000000 of size 134217728 bytes !!!
[C7x_2 ]4.084861 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 69000000 of size 3145728 bytes !!!
[C7x_2 ]4.084879 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 65800000 of size 458752 bytes !!!
[C7x_2 ]4.084896 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 65e00000 of size 16384 bytes !!!
[C7x_2 ]4.084913 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 118000000 of size 134217728 bytes !!!
[C7x_2 ]4.084932 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000001) @ 100000000 of size 134217728 bytes !!!
[C7x_2 ]4.084950 s: MEM: Created heap (DDR_SCRATCH_NON_, id=6, flags=0x00000001) @ 110000000 of size 134217728 bytes !!!
[C7x_2 ]4.084969 s: MEM: Init ... Done !!!
[C7x_2 ]4.084977 s: IPC: Init ... !!!
[C7x_2 ]4.084990 s: IPC: 11 CPUs participating in IPC !!!
[C7x_2 ]4.085005 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_2 ]15.768051 s: IPC: HLOS is ready !!!
[C7x_2 ]15.772491 s: IPC: Init ... Done !!!
[C7x_2 ]15.772507 s: APP: Syncing with 10 CPUs ... !!!
[C7x_2 ]15.871889 s: APP: Syncing with 10 CPUs ... Done !!!
[C7x_2 ]15.871908 s: REMOTE_SERVICE: Init ... !!!
[C7x_2 ]15.872108 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_2 ]15.872131 s:VX_ZONE_INIT:Enabled
[C7x_2 ]15.872142 s:VX_ZONE_ERROR:Enabled
[C7x_2 ]15.872154 s:VX_ZONE_WARNING:Enabled
[C7x_2 ]15.873004 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2[C7x_2 ]15.873069 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_2[C7x_2 ]15.873131 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_3[C7x_2 ]15.873191 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_4[C7x_2 ]15.873246 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_5[C7x_2 ]15.873302 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_6[C7x_2 ]15.873361 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_7[C7x_2 ]15.873419 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_8[C7x_2 ]15.873441 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_2 ]15.873454 s: APP: OpenVX Target kernel init ... !!!
[C7x_2 ]15.874523 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_2 ]15.874546 s: UDMA Copy: Init ... !!!
[C7x_2 ]15.876531 s: UDMA Copy: Init ... Done !!!
[C7x_2 ]15.876550 s: APP: Init ... Done !!!
[C7x_2 ]15.876560 s: APP: Run ... !!!
[C7x_2 ]15.876569 s: IPC: Starting echo test ...
[C7x_2 ]15.876813 s: APP: Run ... Done !!!
[C7x_2 ]15.877276 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[s] c7x_3[.] c7x_4[.][C7x_2 ]15.877323 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[.][C7x_2 ]15.877367 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P][C7x_2 ]15.882000 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P][C7x_2 ]15.882078 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P][C7x_2 ]15.882122 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P][C7x_2 ]15.889489 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P][C7x_2 ]15.931221 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P][C7x_3 ]4.715179 s: CIO: Init ... Done !!!
[C7x_3 ]4.715194 s: ### CPU Frequency = 1000000000 Hz
[C7x_3 ]4.715205 s: CPU is running FreeRTOS
[C7x_3 ]4.715213 s: APP: Init ... !!!
[C7x_3 ]4.715221 s: SCICLIENT: Init ... !!!
[C7x_3 ]4.715347 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_3 ]4.715360 s: SCICLIENT: DMSC FW revision 0x8[C7x_3 ]4.715370 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_3 ]4.715381 s: SCICLIENT: Init ... Done !!!
[C7x_3 ]4.715390 s: UDMA: Init ... !!!
[C7x_3 ]4.716336 s: UDMA: Init ... Done !!!
[C7x_3 ]4.716347 s: MEM: Init ... !!!
[C7x_3 ]4.716359 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 108000000 of size 134217728 bytes !!!
[C7x_3 ]4.716379 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 6a000000 of size 3145728 bytes !!!
[C7x_3 ]4.716397 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 66800000 of size 458752 bytes !!!
[C7x_3 ]4.716414 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 66e00000 of size 16384 bytes !!!
[C7x_3 ]4.716432 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 118000000 of size 134217728 bytes !!!
[C7x_3 ]4.716451 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000001) @ 100000000 of size 134217728 bytes !!!
[C7x_3 ]4.716470 s: MEM: Created heap (DDR_SCRATCH_NON_, id=6, flags=0x00000001) @ 110000000 of size 134217728 bytes !!!
[C7x_3 ]4.716490 s: MEM: Init ... Done !!!
[C7x_3 ]4.716498 s: IPC: Init ... !!!
[C7x_3 ]4.716510 s: IPC: 11 CPUs participating in IPC !!!
[C7x_3 ]4.716525 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_3 ]15.793025 s: IPC: HLOS is ready !!!
[C7x_3 ]15.796879 s: IPC: Init ... Done !!!
[C7x_3 ]15.796894 s: APP: Syncing with 10 CPUs ... !!!
[C7x_3 ]15.871889 s: APP: Syncing with 10 CPUs ... Done !!!
[C7x_3 ]15.871906 s: REMOTE_SERVICE: Init ... !!!
[C7x_3 ]15.872112 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_3 ]15.872135 s:VX_ZONE_INIT:Enabled
[C7x_3 ]15.872145 s:VX_ZONE_ERROR:Enabled
[C7x_3 ]15.872157 s:VX_ZONE_WARNING:Enabled
[C7x_3 ]15.872594 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3[C7x_3 ]15.872701 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_2[C7x_3 ]15.872807 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_3[C7x_3 ]15.872871 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_4[C7x_3 ]15.872932 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_5[C7x_3 ]15.872993 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_6[C7x_3 ]15.873062 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_7[C7x_3 ]15.873133 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_8[C7x_3 ]15.873157 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_3 ]15.873170 s: APP: OpenVX Target kernel init ... !!!
[C7x_3 ]15.873729 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_3 ]15.873744 s: UDMA Copy: Init ... !!!
[C7x_3 ]15.875660 s: UDMA Copy: Init ... Done !!!
[C7x_3 ]15.875677 s: APP: Init ... Done !!!
[C7x_3 ]15.875687 s: APP: Run ... !!!
[C7x_3 ]15.875695 s: IPC: Starting echo test ...
[C7x_3 ]15.875923 s: APP: Run ... Done !!!
[C7x_3 ]15.876276 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[x] c7x_3[s] c7x_4[x][C7x_3 ]15.876734 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[x] c7x_3[s] c7x_4[P][C7x_3 ]15.877277 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P][C7x_3 ]15.882019 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P][C7x_3 ]15.882117 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P][C7x_3 ]15.882162 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P][C7x_3 ]15.889501 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P][C7x_3 ]15.931232 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P][C7x_4 ]5.346438 s: CIO: Init ... Done !!!
[C7x_4 ]5.346452 s: ### CPU Frequency = 1000000000 Hz
[C7x_4 ]5.346464 s: CPU is running FreeRTOS
[C7x_4 ]5.346472 s: APP: Init ... !!!
[C7x_4 ]5.346480 s: SCICLIENT: Init ... !!!
[C7x_4 ]5.346614 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_4 ]5.346628 s: SCICLIENT: DMSC FW revision 0x8[C7x_4 ]5.346638 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_4 ]5.346649 s: SCICLIENT: Init ... Done !!!
[C7x_4 ]5.346657 s: UDMA: Init ... !!!
[C7x_4 ]5.347638 s: UDMA: Init ... Done !!!
[C7x_4 ]5.347649 s: MEM: Init ... !!!
[C7x_4 ]5.347660 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 108000000 of size 134217728 bytes !!!
[C7x_4 ]5.347680 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 6b000000 of size 3145728 bytes !!!
[C7x_4 ]5.347698 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 67800000 of size 458752 bytes !!!
[C7x_4 ]5.347716 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 67e00000 of size 16384 bytes !!!
[C7x_4 ]5.347733 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 118000000 of size 134217728 bytes !!!
[C7x_4 ]5.347752 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000001) @ 100000000 of size 134217728 bytes !!!
[C7x_4 ]5.347770 s: MEM: Created heap (DDR_SCRATCH_NON_, id=6, flags=0x00000001) @ 110000000 of size 134217728 bytes !!!
[C7x_4 ]5.347789 s: MEM: Init ... Done !!!
[C7x_4 ]5.347797 s: IPC: Init ... !!!
[C7x_4 ]5.347810 s: IPC: 11 CPUs participating in IPC !!!
[C7x_4 ]5.347824 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_4 ]15.849309 s: IPC: HLOS is ready !!!
[C7x_4 ]15.852756 s: IPC: Init ... Done !!!
[C7x_4 ]15.852772 s: APP: Syncing with 10 CPUs ... !!!
[C7x_4 ]15.871889 s: APP: Syncing with 10 CPUs ... Done !!!
[C7x_4 ]15.871905 s: REMOTE_SERVICE: Init ... !!!
[C7x_4 ]15.872099 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_4 ]15.872124 s:VX_ZONE_INIT:Enabled
[C7x_4 ]15.872135 s:VX_ZONE_ERROR:Enabled
[C7x_4 ]15.872146 s:VX_ZONE_WARNING:Enabled
[C7x_4 ]15.872599 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4[C7x_4 ]15.872717 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_2[C7x_4 ]15.872821 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_3[C7x_4 ]15.872891 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_4[C7x_4 ]15.872951 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_5[C7x_4 ]15.873013 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_6[C7x_4 ]15.873076 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_7[C7x_4 ]15.873140 s:VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_8[C7x_4 ]15.873161 s:VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_4 ]15.873173 s: APP: OpenVX Target kernel init ... !!!
[C7x_4 ]15.873740 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_4 ]15.873756 s: UDMA Copy: Init ... !!!
[C7x_4 ]15.876047 s: UDMA Copy: Init ... Done !!!
[C7x_4 ]15.876062 s: APP: Init ... Done !!!
[C7x_4 ]15.876072 s: APP: Run ... !!!
[C7x_4 ]15.876081 s: IPC: Starting echo test ...
[C7x_4 ]15.876329 s: APP: Run ... Done !!!
[C7x_4 ]15.876728 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[x] c7x_3[.] c7x_4[s][C7x_4 ]15.876777 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[s][C7x_4 ]15.877284 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[x] mcu3_1[x] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s][C7x_4 ]15.882027 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s][C7x_4 ]15.882130 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s][C7x_4 ]15.882175 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s][C7x_4 ]15.889514 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s][C7x_4 ]15.931244 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s][130.011564] Initializing XFRM netlink socket
[130.922194] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[130.937077] Bridge firewalling registered
[131.297637] process 'docker/tmp/qemu-check267263808/check' started with executable stack

,

Cherry Zhou：

好的我们跟进给工程师了。

,

Cherry Zhou：

请更正以下配置"Board_serdesCfgSgmii_serdes1"：

– serdesLane0EnableParams.numLanes = 0x2;- serdesLane0EnableParams.laneMask = 0x3;

+ serdesLane0EnableParams.numLanes = 0x;1 // one lane select+ serdesLane0EnableParams.laneMask = 0x2; //Lane1 enable- serdesLane0EnableParams.phyInstanceNum    = BOARD_SERDES_LANE_SELECT_CPSW;+ serdesLane0EnableParams.phyInstanceNum    = 0; // It is IP for IP instance select in SerDes Lane only when same SerDes lane has two ethernet ports configurations it will be vary as per port being used . (Ex: SerDes2 Lane has Port-1(IP1) and Poer-7 (IP0), default Port1 is enabled from SerDes2 so it is set to 1)

此外，对于除 Lane1 (从 SerDes1启用端口4)之外的所有通道，删除"CSL_serdesIPSelect"调用。 

,

yk z：

所以修改成下面这样

Board_STATUS Board_CfgSgmii_serdes1(void)
{CSL_SerdesResult result;CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;CSL_SerdesLaneEnableParams serdesLane0EnableParams= {0};printf("%s %d \n",__func__,__LINE__);memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));/* SGMII Config */serdesLane0EnableParams.serdesInstance= (CSL_SerdesInstance)CSL_TORRENT_SERDES1;serdesLane0EnableParams.baseAddr= CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;serdesLane0EnableParams.refClock= CSL_SERDES_REF_CLOCK_100M;serdesLane0EnableParams.refClkSrc= CSL_SERDES_REF_CLOCK_INT0;serdesLane0EnableParams.linkRate= CSL_SERDES_LINK_RATE_1p25G;serdesLane0EnableParams.numLanes= 0x1;serdesLane0EnableParams.laneMask= 0x2;serdesLane0EnableParams.SSC_mode= CSL_SERDES_NO_SSC;serdesLane0EnableParams.phyType= CSL_SERDES_PHY_TYPE_SGMII;serdesLane0EnableParams.operatingMode= CSL_SERDES_FUNCTIONAL_MODE;serdesLane0EnableParams.phyInstanceNum= 0;//BOARD_SERDES_LANE_SELECT_CPSW;serdesLane0EnableParams.pcieGenType= CSL_SERDES_PCIE_GEN3;serdesLane0EnableParams.laneCtrlRate[0]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[0]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[1]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[1]= CSL_SERDES_LOOPBACK_DISABLED;printf("%s %d \n",__func__,__LINE__);CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);printf("%s %d \n",__func__,__LINE__);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,1U);printf("%s %d \n",__func__,__LINE__);result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.baseAddr,serdesLane0EnableParams.refClock,serdesLane0EnableParams.refClkSrc,serdesLane0EnableParams.serdesInstance,serdesLane0EnableParams.phyType);printf("%s %d \n",__func__,__LINE__);if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}printf("%s %d \n",__func__,__LINE__);/* Assert PHY reset and disable all lanes */CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);printf("%s %d \n",__func__,__LINE__);/* Load the Serdes Config File */result = CSL_serdesEthernetInit(&serdesLane0EnableParams);/* Return error if input params are invalid */if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}printf("%s %d \n",__func__,__LINE__);/* Common Lane Enable API for lane enable, pll enable etc */laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);if (laneRetVal != 0){return BOARD_FAIL;}printf("%s %d \n",__func__,__LINE__);return BOARD_SOK;
}

修改后好像没有PLL的打印

下面,请一一回答我的问题,谢谢

问题1:

类似,配置在serdes2 lane 0-3的port 5 6 7 8 以下代码

static Board_STATUS Board_CfgSgmii_serdes2(void)
{CSL_SerdesResult result;CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;CSL_SerdesLaneEnableParams serdesLane0EnableParams= {0};memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));/* SGMII Config */serdesLane0EnableParams.serdesInstance= (CSL_SerdesInstance)CSL_TORRENT_SERDES2;serdesLane0EnableParams.baseAddr= CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;serdesLane0EnableParams.refClock= CSL_SERDES_REF_CLOCK_100M;serdesLane0EnableParams.refClkSrc= CSL_SERDES_REF_CLOCK_INT0;serdesLane0EnableParams.linkRate= CSL_SERDES_LINK_RATE_1p25G;serdesLane0EnableParams.numLanes= 0x4;serdesLane0EnableParams.laneMask= 0xf;serdesLane0EnableParams.SSC_mode= CSL_SERDES_NO_SSC;serdesLane0EnableParams.phyType= CSL_SERDES_PHY_TYPE_SGMII;serdesLane0EnableParams.operatingMode= CSL_SERDES_FUNCTIONAL_MODE;serdesLane0EnableParams.phyInstanceNum= 0;//SERDES_LANE_SELECT_CPSW;serdesLane0EnableParams.pcieGenType= CSL_SERDES_PCIE_GEN3;serdesLane0EnableParams.laneCtrlRate[0]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[0]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[1]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[1]= CSL_SERDES_LOOPBACK_DISABLED;CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,0U);CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,1U);CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,2U);CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,3U);result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.baseAddr,serdesLane0EnableParams.refClock,serdesLane0EnableParams.refClkSrc,serdesLane0EnableParams.serdesInstance,serdesLane0EnableParams.phyType);if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}/* Assert PHY reset and disable all lanes */CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);/* Load the Serdes Config File */result = CSL_serdesEthernetInit(&serdesLane0EnableParams);/* Return error if input params are invalid */if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}/* Common Lane Enable API for lane enable, pll enable etc */laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);if (laneRetVal != 0){return BOARD_FAIL;}return BOARD_SOK;
}

问题2:

如何确保serdes 配置成功

没有以下这样的打印,就认为配置成功了?

CpswMacPort_setSgmiiInterface: MAC 5: SERDES PLL is not locked 

,

Cherry Zhou：

您好，请查看工程师的以下答复：

You have to add below for all lanes. In case of Board_CfgSgmii_serdes2() it is missing for Lane2, Lane3.serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;Also, make sure that SerDes clock is configured similar to "EthFwBoard_configTorrentClks1()".

yk z 说：

问题2:

如何确保serdes 配置成功

没有以下这样的打印,就认为配置成功了?

CpswMacPort_setSgmiiInterface: MAC 5: SERDES PLL is not locked 

If phy is connected to Link partner, will get Link Up message. It will confirm the configuration fine.We can check SerDes registers to confirm configuration was fine or not. If no prints like No PLL lock it might be locked.

,

yk z：

You have to add below for all lanes. In case of Board_CfgSgmii_serdes2() it is missing for Lane2, Lane3.serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;Also, make sure that SerDes clock is configured similar to "EthFwBoard_configTorrentClks1()"

意思是：

我的Board_CfgSgmii_serdes2函数中，我的目的是需要设置serdes 2的 lan 0 ,lan 1,lan 2,lan 3

函数中缺少了lan2 ,lan3，需要加上以下

serdesLane0EnableParams.laneCtrlRate[2]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[2]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[3]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[3]= CSL_SERDES_LOOPBACK_DISABLED;

变成（帮忙review一下，thx)：

static Board_STATUS Board_CfgSgmii_serdes2(void)
{CSL_SerdesResult result;CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;CSL_SerdesLaneEnableParams serdesLane0EnableParams= {0};memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));/* SGMII Config */serdesLane0EnableParams.serdesInstance= (CSL_SerdesInstance)CSL_TORRENT_SERDES2;serdesLane0EnableParams.baseAddr= CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;serdesLane0EnableParams.refClock= CSL_SERDES_REF_CLOCK_100M;serdesLane0EnableParams.refClkSrc= CSL_SERDES_REF_CLOCK_INT0;serdesLane0EnableParams.linkRate= CSL_SERDES_LINK_RATE_1p25G;serdesLane0EnableParams.numLanes= 0x4;serdesLane0EnableParams.laneMask= 0xf;serdesLane0EnableParams.SSC_mode= CSL_SERDES_NO_SSC;serdesLane0EnableParams.phyType= CSL_SERDES_PHY_TYPE_SGMII;serdesLane0EnableParams.operatingMode= CSL_SERDES_FUNCTIONAL_MODE;serdesLane0EnableParams.phyInstanceNum= 0;//SERDES_LANE_SELECT_CPSW;serdesLane0EnableParams.pcieGenType= CSL_SERDES_PCIE_GEN3;serdesLane0EnableParams.laneCtrlRate[0]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[0]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[1]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[1]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[2]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[2]= CSL_SERDES_LOOPBACK_DISABLED;serdesLane0EnableParams.laneCtrlRate[3]= CSL_SERDES_LANE_FULL_RATE;serdesLane0EnableParams.loopbackMode[3]= CSL_SERDES_LOOPBACK_DISABLED;CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);/* Select the IP type, IP instance num, Serdes Lane Number */CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,0U);CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,1U);CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,2U);CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.phyType,serdesLane0EnableParams.phyInstanceNum,serdesLane0EnableParams.serdesInstance,3U);result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,serdesLane0EnableParams.baseAddr,serdesLane0EnableParams.refClock,serdesLane0EnableParams.refClkSrc,serdesLane0EnableParams.serdesInstance,serdesLane0EnableParams.phyType);if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}/* Assert PHY reset and disable all lanes */CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);/* Load the Serdes Config File */result = CSL_serdesEthernetInit(&serdesLane0EnableParams);/* Return error if input params are invalid */if (result != CSL_SERDES_NO_ERR){return BOARD_FAIL;}/* Common Lane Enable API for lane enable, pll enable etc */laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);if (laneRetVal != 0){return BOARD_FAIL;}return BOARD_SOK;
}

,

Cherry Zhou：

对的，以上具有串行器/解串器配置的文本文件适用于在 SGMII 模式下配置port 5 6 7 8。 

,

yk z：

这边

serdes1 lane 1已经link上了,但是没有ping通

,

yk z：

tx rx 的差分信号

,

Cherry Zhou：

已跟进给工程师，请关注英文论坛的答复。

,

yk z：

请问一下如下代码的配置，会影响dhcp或ping包的流程嘛，每一个代表什么意思，可以说明一下，？

\ti-processor-sdk-rtos-j784s4-evm-08_06_00_14\vision_apps\utils\ethfw\src\app_ethfw_freertos.c

static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
{{.remoteCoreId = IPC_MPU1_0,.portId= ETHREMOTECFG_SWITCH_PORT_0,},{.remoteCoreId = IPC_MCU2_1,.portId= ETHREMOTECFG_SWITCH_PORT_1,},{.remoteCoreId = IPC_MPU1_0,.portId= ETHREMOTECFG_MAC_PORT_5,},{.remoteCoreId = IPC_MCU2_1,.portId= ETHREMOTECFG_MAC_PORT_4,},};