TI中文支持网Part Number:ADS54J60
In the process of configuring ADS54J60 to collect data and establish an 8224 link with JESD204B, strictly follow the sequence of ADC hardware reset, SPI write, and JESD204B core reset. From the waveform data captured by ILA (online logic analyzer), it should The link establishment has been completed, and the JESD status indication registers 0x038 and 0x03C also indicate that the synchronization and link establishment have been completed (output 0x00010001 and 0xeeeeeeee respectively), but after the ADC sends K28.5 and ILA data, all sent Valid data are all 0. I see that other people on the forum have encountered the same problem, but he didn't give a specific solution. Hope to get official technical help!
At the same time, I found a problem: After writing the 0x68h register on page 6100, it cannot be read back correctly, and the read back data is always 0, and the rest of the registers on page 6100 and page 6A00 (whether they are readable or writable registers) have this Such problems, but the 6900-page register with the same read and write timing can read back the written data normally, I think the problem may be here. In addition: I will confirm that I have switched to the corresponding page before each readback
My register writing sequence is as shown in the figure below. After each address switch, I wait for 32ms, and I wait for 160ms after PLL reset:
Kailyn Chen：
您好，您的这个问题和https://e2echina.ti.com/support/data-converters/f/data-converters-forum/750555/ads54j60-jesd204b-0 重复了，为了更好的解决您的问题，我同事已经将您的问题升级到英文E2E了，并且会尽快给您答复的。
