TI中文支持网Part Number:LMK04832
LMK04832用SDCLKOUT5输出两路CMOS时钟，想要把时钟频率调到1.25GHz或者2.5GHz，发现输出时钟超过11.1GHz之后就开始衰减，调到1.25GHz时衰减已经超过10dB,切换CMOS(Norn/norm)\CMOS(norm/inv)等多种输出配置，衰减程度均不一样，可能是什么原因，手头没有评估板，没法验证。
Amy Luo：
您好，我稍后会看下您的问题，给您带来不便很抱歉
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xiang gang：
非常感谢
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Amy Luo：
很抱歉回复这么迟!
为更加有效地解决您的问题，我已将此问题发布在E2E英文技术论坛上，请资深的英文论坛工程师为您提供帮助。帖子链接如下，您也可以关注帖子，以方便查看或追问后续疑问。
英文论坛对应子论坛链接：https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1226302/lmk04832-cmos-output-amplitude-attenuation
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Amy Luo：
您好，我将英文工程师的回复贴在下面，大体意思是这是由其输出结构决定的，是正常现象；LMK04832上的其他输出格式使用bipolar transistors（双极晶体管）而不是MOSFET，并且双极晶体管在其有源使用模式下具有极低的寄生电容。由于这种较低的电容，即使总电流负载较低，像LVPECL和CML这样的输出格式在较高频率下的衰减也往往要小得多，因为在转换速率方程中，C的比例比I低得多。
LVCMOS output buffers are, as the name suggests, low-voltage complementary MOSFET outputs. This means that the output stage is derived from a P-channel and N-channel MOSFET in a "totem pole" configuration, see below.
These MOSFETs have some intrinsic parasitic capacitances from gate to drain, gate to source, and source to drain, which vary as a function of applied VGS and VDS voltages. But these capacitances can easily be in the picofarad range in terms of order of magnitude.
Additionally, each MOSFET has some maximum short-circuit current it can supply based on the gate-source potential that can be applied internally, where the MOSFET hits the linear region and begins to behave like a linear resistor. This might be a few tens of mA.
In order to make for a convenient and approximately correct example calculation, let's say 5pF is the parasitic capacitance and 50mA is the short-circuit current achievable in the MOSFET linear region – this is reasonably close to the actual values for the LMK04832.
Now, consider a 3.3V sine wave at 1GHz. Taking a basic derivative, we know the maximum slew rate of just this sine wave is 2π*Vpk*F, which at 1GHz works out to about 10V/ns. Incidentally, if we take 5pF and 50mA, and consider that I = C * dV/dT, we find that dV/dT = 50mA / 5pF = 10V/ns. Since our output current is limited by the drain-source voltage during the short circuit condition, our output slew rate can never be faster than what is required for a 3.3V 1GHz sine wave.
Finally, recall that to get a sharp square wave, we require summing the Fourier series of the fundamental and several of its odd harmonics.
At 1GHz, we are able to get a reasonable slew rate on the fundamental, but the harmonics at 3GHz, 5GHz, 7GHz, etc. all require 3x, 5x, 7x the slew rate for a comparable amplitude sine wave. We cannot supply enough current to achieve comparable amplitude in the higher order harmonics, and so the waveform appears attenuated because the higher-order harmonics that give it a characteristic square shape are attenuated. Edited: I remember there is a factor of 1/n in the Fourier series summation, so actually the slew rate requirements remain equivalent: the amplitude of the 3rd order harmonic at 3GHz is 1/3 of the fundamental, so the slew rate should be sufficient for a decent square wave up to the limits of attenuation. However, the impedance of the parasitic capacitance drops dramatically at higher frequency, and the short circuit MOSFET into a parasitic capacitance looks like a low-pass filter; so the amplitude of the higher-order harmonics is attenuated by 20log(1/n) vs 1/n required for each harmonic of the square wave. And above 1GHz, we would still expect slew rate limitations to impact amplitude.
This is one of the reasons why the datasheet lists the maximum output frequency of LVCMOS as no less than 250MHz – while we can reasonably expect a decently square square wave at 250MHz, above this frequency we would expect a gradual transition to increasingly attenuated sine wave.
There are other reasons, particularly reflections – CMOS output stages have variable impedance as a function of the VDS voltage across the active stage (especially during the transition from linear to saturation regions), which makes higher frequency CMOS signals difficult to terminate at the receiver without a significant reflection component; in continuous operation this creates a standing wave that tends to disrupt the normally monotonic CMOS edges. Careful design with low-capacitance MOSFETs and some resistive damping to attenuate the reflections can sometimes allow for higher frequency CMOS signaling, but generally only at very low voltages where the MOSFET capacitances can be smaller, or within silicon ASICs where the distances between source and load (and therefore the reflections) are negligible and the capacitance is extremely low relative to the actual loading.
In other words, using LVCMOS output format on LMK04832 above 250MHz is not recommended.
Other output formats on LMK04832 use bipolar transistors instead of MOSFETs, and the bipolar transistors have extremely low parasitic capacitance in their active usage mode. Output formats like LVPECL and CML tend to attenuate much less at higher frequency thanks to this lower capacitance, even if the total current load is lower, because C scales much, much lower than I in the slew rate equation (low hundreds of femtofarads is >10x capacitance reduction, vs maybe a 2x or 3x reduction in drive current).
