TI中文支持网Part Number:TDA2SX
尊敬的工程师，您好
我在使用TDA2的以太网功能，原本PROCESS_RADAR_SDK默认NDK是运行在IPU1_1，现在需要使用TCP往PC传输大数据，因此我将NDK定义到了A15_0的内核运行，网络1000Mbps速率协商正常，TCP连接正常，但是发现吞吐率太慢，通过wireShake抓包之后发现，发送4MB的数据时，都会在数据发到90kB到100kB之间产生几帧的连续丢失，造成这几帧不断的re transmission，除了这几帧丢失之外，其余数据发送正常。
因此我想问一下，将NDK配置到A15_0需要注意什么，有没有配置项目被我遗漏了，针对以上现象我该如何排查？麻烦工程师给我一些指导建议，谢谢！
?? ?：
我主要做了如下修改：
1、 在tda2xx_cascade_bios_radar 目录下的cfg.mk文件里 设置 NDK_PROC_TO_USE=a15_0
2、重新生成usecases里的相关priv.c和priv.h文件，主要是把NetworkTx (IPU1_1)修改为NetworkTx (A15)
3、在文件mem_segment_definition_bios.xs中适当的调整了增加了NDK_DATA_SIZE 和 A15_0_DATA_SIZE, 具体如下：
/**======== mem_segment_definition.xs ========*======== Single file for the memory map configuration of all cores =========*/function getMemSegmentDefinition_external(core) {KB=1024;MB=KB*KB;DDR3_ADDR= 0x80000000;DDR3_SIZE= 512*MB;/** In case of ECC_FFI_INCLUDE, DDR3_BASE_ADDR_1 and DDR3_BASE_SIZE_1* are hard-coded in as values of gIpcNonCachedDataAddr and* gIpcNonCachedDataSize in Ipu1_0.cfg* If this DDR3_BASE_SIZE_0 is changed, updateIpu1_0.cfg*/DDR3_BASE_ADDR_0= DDR3_ADDR;DDR3_BASE_SIZE_0= 507*MB;/* The start address of the second mem section should be 16MB aligned.* This alignment is a must as a single 16MB mapping is used for EVE* to map SR0, REMOTE_LOG_MEM sections.* tlb_config_eveX.c need to be modified otherwise*/DDR3_BASE_ADDR_1= DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0;DDR3_BASE_SIZE_1= DDR3_SIZE - DDR3_BASE_SIZE_0;//if(core=="ipu1_1" || core=="ipu1_0" || core=="ipu2" || core=="a15_0")//{/*for ipu1_0, ipu1_1, ipu2 DDR3_BASE_ADDR_1 should be*in non-cached virtual address of*DDR3_BASE_ADDR_1 + 512*MB*/DDR3_BASE_ADDR_1= DDR3_BASE_ADDR_1+512*MB;//}DSP1_L2_SRAM_ADDR= 0x40800000;DSP1_L2_SRAM_SIZE= 288*KB;DSP2_L2_SRAM_ADDR= 0x41000000;DSP2_L2_SRAM_SIZE= 288*KB;EVE1_SRAM_ADDR= 0x42000000;EVE1_SRAM_SIZE= 1*MB;EVE2_SRAM_ADDR= 0x42100000;EVE2_SRAM_SIZE= 1*MB;EVE3_SRAM_ADDR= 0x42200000;EVE3_SRAM_SIZE= 1*MB;EVE4_SRAM_ADDR= 0x42300000;EVE4_SRAM_SIZE= 1*MB;TOTAL_MEM_SIZE= (DDR3_SIZE);/* First 512 MB - cached *//* EVE vecs space should be align with 16MB boundary, and if possible try to fit* the entire vecs+code+data in 16MB section. In this case a single TLB map would* be enough to map vecs+code+data of an EVE.* tlb_config_eveX.c need to be modified if any of these EVE memory sections or* SR1_FRAME_BUFFER_MEM section is modified.*//* EVE self-branch instruction block - EVE1_VECS* In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.* This could overwrites the code/data loaded at 0x80000000.* So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for* EVE self-branch instruction if no AppImage for EVE.* If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,* and hence we did not observe any issue.* If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,* if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000*/EVE1_VECS_SIZE= 0.5*MB;EVE1_CODE_SIZE=2*MB;EVE1_DATA_SIZE=13.5*MB;EVE2_VECS_SIZE= 0.5*MB;EVE2_CODE_SIZE=2*MB;EVE2_DATA_SIZE=13.5*MB;EVE3_VECS_SIZE= 0.5*MB;EVE3_CODE_SIZE=2*MB;EVE3_DATA_SIZE=13.5*MB;EVE4_VECS_SIZE= 0.5*MB;EVE4_CODE_SIZE=2*MB;EVE4_DATA_SIZE=13.5*MB;NDK_DATA_SIZE=8*MB;if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes"){IPU1_1_CODE_SIZE= 2.5*MB;IPU1_1_DATA_SIZE= 12.5*MB;IPU1_0_CODE_SIZE=6*MB;IPU1_0_DATA_SIZE=12*MB;}else{IPU1_1_CODE_SIZE= 2.5*MB;IPU1_1_DATA_SIZE= 12.5*MB;IPU1_0_CODE_SIZE=6*MB;IPU1_0_DATA_SIZE=16*MB;}IPU2_CODE_SIZE=2*MB;IPU2_DATA_SIZE=7*MB;DSP1_CODE_SIZE=6*MB;DSP1_DATA_SIZE=14*MB;DSP1_DATA_SIZE_2=1*MB;DSP2_CODE_SIZE=4*MB;DSP2_DATA_SIZE=14*MB;DSP2_DATA_SIZE_2=1*MB;/* A15_0_CODE_SIZE reduced since it is not used in .bld file.* Check .bld for details. Originally 2 + 14 MB.*/A15_0_DATA_SIZE=43.5*MB;if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes"){A15_0_DATA_SIZE_INC=101*MB /* in MB */A15_0_DATA_SIZE=(A15_0_DATA_SIZE + A15_0_DATA_SIZE_INC);}if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes"){/* Ensure ECC regions are 64kB aligned */SR1_FRAME_BUFFER_SIZE= 297.5*MB;SR1_BUFF_ECC_ASIL_SIZE=1*MB;SR1_BUFF_ECC_QM_SIZE=40*MB;SR1_BUFF_NON_ECC_ASIL_SIZE=1*MB;}else{SR1_BUFF_ECC_ASIL_SIZE=4*KB;SR1_BUFF_ECC_QM_SIZE=4*KB;SR1_BUFF_NON_ECC_ASIL_SIZE=4*KB;SR1_FRAME_BUFFER_SIZE= 305.5*MB - (SR1_BUFF_ECC_ASIL_SIZE + SR1_BUFF_ECC_QM_SIZE + SR1_BUFF_NON_ECC_ASIL_SIZE);if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes"){SR1_FRAME_BUFFER_SIZE= SR1_FRAME_BUFFER_SIZE - A15_0_DATA_SIZE_INC;}}/* Second 512 MB - non-cached *//* The start address of the second mem section should be 16MB aligned.* This alignment is a must as a single 16MB mapping is used for EVE* to map SR0, REMOTE_LOG_MEM sections.* tlb_config_eveX.c need to be modified otherwise*/REMOTE_LOG_SIZE=160*KB;SYSTEM_IPC_SHM_SIZE=480*KB;SYSTEM_AUTOSAR_IPC_SHM_SIZE =512*KB;LINK_STATS_SIZE=256*KB;HDVPSS_DESC_SIZE= 1024*KB;SR0_SIZE=128*KB;OPENVX_SHM_SIZE= 1984*KB;EEPROM_PARAM_SIZE=64*KB;if((java.lang.System.getenv("OPENCL_INCLUDE") == "yes")){/* when OpenCL is enabled we need more SR0 space*/SR0_SIZE=2*MB;}4、使用MAC0 ，并设置了静态IP；
现象描述：如果NDK配置在IPU1_1中运行，千兆网络通信正常，每帧1MB数据，连续发送，并不会出现丢帧现象；
但是如果通过以上配置，将NDK配置在A15内核中运行，千兆网络能够正常连接，但是比如连续发送4帧，每帧1MB的数据，
每次都会在发送第一帧1MB处的90kB-100kB之间出现丢帧，所丢的这些帧通过TCP底层的重发机制最后也都能重发成功，但是这样会导致吞吐率下降，
由于在IPU1_1中运行正常，在A15中才会出现此现象，因此我感觉是程序里哪儿配置不对，麻烦工程师给指导一下，谢谢。
wireshake抓包信息如下：
其中192.168.31.100是PC机。
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Nancy Wang：
我们稍后会将您的帖子升级到E2E，会有产品线专家给您提供支持。
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?? ?：
您好，产品线专家有回复吗？
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Cherry Zhou：
您好，暂时还没有，我们来催促一下，英文论坛的链接也给您贴在下面：
e2e.ti.com/…/tda2sx-tcp-sending-large-data-can-cause-packet-loss-at-a-fixed-location
