TI中文支持网Part Number:ADS8686S
Hi, Technical Support Team,
I'd like to use ADS8686S for analog acquisition with FPGA，I have some questions about power-supply sequence and RESET pin.
In ADS8686 Datasheet(REV C) Page106, it syas that "Hold RESET low until both supplies are stabilized." In my current hardware design, ads8686s reset pin is pulled HIGH by pull-up circuit when powered on.
Q1:
Why should hold reset low until both supplies are stabilized?
Q2:
Will it cause any problem if Hold reset HIGH before both supplies are stabilized? Will it stuck?
Q3:
What else can I to avoiding potential issues for my current hardware design? For example, If ads8686 stuck, Powerup reset or Full Reset can work?
Amy Luo：
Hi Kong,
1、During the power on process, the state of some pins ( such as HW_RNGSELx, REFSEL, SER/BYTE/ PAR, DB9/BYTESEL, and DB4/ SER1W pins ) may be in an uncertain state. During the power on process, lowering the reset and releasing it after the power supply stabilizes can make the state of these pins in a certain state. Please refer to the description in the screenshot of the datasheet for details:
2、The device will not get stuck, but the pin logic level that may be latched may not be the value you expected or the value set by the circuit.
3、After powering on, you can perform a full reset operation, which should solve the above problem.
