TI中文支持网Part Number:OPA140Other Parts Discussed in Thread: OPA2140, OPA4140
; Translated with ADS Netlist Translator (*) 550.shp Jul 24 2021
;
;Mapping SPICE functions file to the Netlist
#ifndef SPCFUNCTIONS_FILE
#define SPCFUNCTIONS_FILE
#include "$HPEESOF_DIR/links/spice/spicefunctions.net"
#endif
;
;$
; OPAx140
;****************************************************************************
; (C) Copyright 2022 Texas Instruments Incorporated. All rights reserved.
;****************************************************************************
;* This model is designed as an aid for customers of Texas Instruments.
;* TI and its licensors and suppliers make no warranties, either expressed
;* or implied, with respect to this model, including the warranties of
;* merchantability or fitness for a particular purpose. The model is
;* provided solely on an "as is" basis. The entire risk as to its quality
;* and performance is with the customer
;****************************************************************************
;
; This model is subject to change without notice. Texas Instruments
; Incorporated is not responsible for updating this model.
;
;****************************************************************************
;
;* Released by: Online Design Tools, Texas Instruments Inc.
; Part: OPAx140
; Date: 25FEB2022
; Model Type: Generic (suitable for all analysis types)
; EVM Order Number: N/A
; EVM Users Guide: N/A
; Datasheet: SBOS498E – JULY 2010 – REVISED JULY 2021
; Created with Green-Williams-Lis Op Amp Macro-model Architecture
;
; Model Version: Final 1.5
;
;****************************************************************************
;
; Updates:
;
; Final 1.5
; 1. Moved the R_NOISELESS .model definition to main subckt.
;
; Final 1.4
; 1. Modified the capacitor(C14) value from 1F to 2uF in GND Float-IQ block
; to resolve the convergence issue in single and asymmetric supply test.
; 2. Updated Aol to match the GBW as per the datasheet.
; 3. Updated CLAW Curves to match the datasheet.
; 4. Updated the model name from OPA140 to OPAx140.
;
; Final 1.3
; Updated with unique subckt name, vos drift, inoise and edits in claw block
;
; Final 1.2
; Release to Web.
;
;****************************************************************************
; Model Usage Notes:
; 1. The following parameters are modeled:
; a. OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)
; b. UNITY GAIN BANDWIDTH (GBW)
; c. INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)
; d. POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)
; e. DIFFERENTIAL INPUT IMPEDANCE (Zid)
; f. COMMON-MODE INPUT IMPEDANCE (Zic)
; g. OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)
; h. OUTPUT CURRENT THROUGH THE SUPPLY (Iout)
; i. INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)
; j. INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)
; k. OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)
; l. SHORT-CIRCUIT OUTPUT CURRENT (Isc)
; m. QUIESCENT CURRENT (Iq)
; n. SETTLING TIME VS. CAPACITIVE LOAD (ts)
; o. SLEW RATE (SR)
; p. SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD
; q. LARGE SIGNAL RESPONSE
; r. OVERLOAD RECOVERY TIME (tor)
; s. INPUT BIAS CURRENT (Ib)
; t. INPUT OFFSET CURRENT (Ios)
; u. INPUT OFFSET VOLTAGE (Vos)
; v. INPUT OFFSET VOLTAGE VS. TEMPERATURE (Vos Drift)
; w. INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
; x. INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)
; y. INPUT/OUTPUT ESD CELLS (ESDin, ESDout)
; 2. OPAx140 model is available in single core(OPA140), dual core(OPA2140)
; and quad core(OPA4140).
;****************************************************************************
define opax140 ( "in+" "in-" vcc vee out)
;****************************************************************************
C:c_c1 n3294772 n3294776 C=2.273p
C:c_c10 n3294626 n3294630 C=3.798u
C:c_c100 n43441421 mid C=3.882p
C:c_c101 n43625331 mid C=176.8f
C:c_c13 n2992397 0 C=1f
C:c_c14 0 n2992375 C=2u
C:c_c15 n2992413 0 C=1f
C:c_c16 n2991741 mid C=1f
C:c_c17 n2991765 mid C=1f
C:c_c18 n2991811 mid C=1f
C:c_c19 n2991831 mid C=1f
C:c_c20 n2991907 mid C=1f
C:c_c21 n2991925 mid C=1f
C:c_c22 mid n2991969 C=1f
C:c_c23 n2992033 mid C=1f
C:c_c24 n2992029 mid C=1f
C:c_c25 n2992093 mid C=1p
C:c_c26 n2992099 mid C=1p
C:c_c27 sw_ol_opax140 mid C=100p
C:c_c29 vimon mid C=1n
C:c_c30 vout_s mid C=1n
C:c_c4 n2991657 mid C=1f
C:c_c5 clamp mid C=38.6n
C:c_c70 vclp mid C=100p
C:c_c72 n4031911 mid C=7.96e-16
C:c_c74 n3827259 n3828449 C=28.94f
C:c_c77 n3850714 n2991581 C=3.003n
C:c_c89 n4029618 n4029628 C=2.303p
C:c_c91 n40409811 mid C=6.366p
C:c_c93 n4243633 n2991579 C=1.224n
C:c_c94 n3294524 mid C=7.96e-16
C:c_c99 n4303995 n4304005 C=8.842f
C:c_c_com0 esdp mid C=7p
C:c_c_com1 mid esdn C=7p
C:c_c_diff esdn esdp C=10p
SDD:e_e1 n2992375 0 mid 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
SDD:e_e3 out mid n2992163 mid I[1,0]=0 F[2,0]=(1*_v1)-_v2
SDD:e_e4 cl_clamp mid n3294618 mid I[1,0]=0 F[2,0]=(1*_v1)-_v2
SDD:g_g1 esdp mid n3294772 mid I[1,0]=0 I[2,0]=-2.013m*_v1
SDD:g_g12 n3294524 mid claw_clamp mid I[1,0]=0 I[2,0]=-1m*_v1
SDD:g_g13 claw_clamp mid cl_clamp mid I[1,0]=0 I[2,0]=-1m*_v1
SDD:g_g16 n3294630 mid n3201092 mid I[1,0]=0 I[2,0]=-255.4*_v1
SDD:g_g18 vcc 0 vcc_b 0 I[1,0]=0 I[2,0]=-1*_v1
SDD:g_g19 vee 0 vee_b 0 I[1,0]=0 I[2,0]=-1*_v1
SDD:g_g2 n2991553 mid n2991563 n2991555 I[1,0]=0 I[2,0]=-1m*_v1
SDD:g_g20 n2992033 mid vcc_clp mid I[1,0]=0 I[2,0]=-1m*_v1
SDD:g_g21 n2992029 mid vee_clp mid I[1,0]=0 I[2,0]=-1m*_v1
SDD:g_g22 n2992295 mid n2992299 mid I[1,0]=0 I[2,0]=-1*_v1
SDD:g_g23 n2992331 mid n2992323 mid I[1,0]=0 I[2,0]=-1*_v1
SDD:g_g39 cl_clamp n2992235 n3294626 mid I[1,0]=0 I[2,0]=-90.9091*_v1
SDD:g_g4 vcc_b mid n3850714 mid I[1,0]=0 I[2,0]=-283.019m*_v1
SDD:g_g41 n4029628 mid n4031911 mid I[1,0]=0 I[2,0]=-1u*_v1
SDD:g_g5 n2991581 n2991579 n2991587 n2991583 I[1,0]=0 I[2,0]=-1m*_v1
SDD:g_g59 n4029666 mid n4029618 mid I[1,0]=0 I[2,0]=-1.165*_v1
SDD:g_g6 clamp mid vsense mid I[1,0]=0 I[2,0]=-1m*_v1
SDD:g_g61 n4040935 mid n4040957 mid I[1,0]=0 I[2,0]=-1*_v1
SDD:g_g63 vee_b mid n4243633 mid I[1,0]=0 I[2,0]=-269.231m*_v1
SDD:g_g64 n4031911 mid n3294524 mid I[1,0]=0 I[2,0]=-1u*_v1
SDD:g_g69 n3294776 mid n4303995 mid I[1,0]=0 I[2,0]=-1*_v1
SDD:g_g70 n4304005 mid n2991553 mid I[1,0]=0 I[2,0]=-27.7778*_v1
SDD:g_g71 vsense mid n4344090 mid I[1,0]=0 I[2,0]=-1*_v1
SDD:g_g72 n4362495 mid n3827259 mid I[1,0]=0 I[2,0]=-1*_v1
I_Source:i_i_b n2991573 mid Idc=500f
I_Source:i_i_os esdn mid Idc=1f
I_Source:i_i_q vcc vee Idc=1.8m
r_noiseless:r_r15 n2991583 n2991563 R=1m
r_noiseless:r_r16 n2991587 n2991583 R=1k
r_noiseless:r_r167 n3294618 vclp R=100
r_noiseless:r_r17 n2991619 esdn R=1m
r_noiseless:r_r171 mid n4031911 R=1M
r_noiseless:r_r176 mid n3827259 R=1
r_noiseless:r_r178 n3828449 n3827259 R=10k
r_noiseless:r_r179 mid n3828449 R=55.3042
r_noiseless:r_r18 mid n2991623 R=1T
r_noiseless:r_r187 n2991581 n3850714 R=100M
r_noiseless:r_r189 mid n3850714 R=1
r_noiseless:r_r19 mid n2991635 R=1T
r_noiseless:r_r190 mid n2991581 R=35.3333
r_noiseless:r_r20 n2991643 mid R=1
r_noiseless:r_r209 mid n3201092 R=1
r_noiseless:r_r21 n2991657 n2991643 R=1m
r_noiseless:r_r22 mid n2991667 R=1M
r_noiseless:r_r223 n4029628 n4029618 R=10k
r_noiseless:r_r224 mid n4029618 R=1
r_noiseless:r_r225 mid n4029628 R=60.61k
r_noiseless:r_r227 n4040935 n3201092 R=31.6667k
r_noiseless:r_r228 n40409811 n4040935 R=10k
r_noiseless:r_r23 mid clamp R=1M
r_noiseless:r_r230 n2991579 n4243633 R=100M
r_noiseless:r_r233 mid n2991579 R=37.1429
r_noiseless:r_r234 mid n4243633 R=1
r_noiseless:r_r235 mid n3294524 R=1M
r_noiseless:r_r24 mid vsense R=1k
r_noiseless:r_r246 n4304005 n4303995 R=100M
r_noiseless:r_r247 mid n4303995 R=1
r_noiseless:r_r248 mid n4304005 R=3.734M
r_noiseless:r_r249 mid n2991553 R=1
r_noiseless:r_r250 n4029666 n4344090 R=5.472k
r_noiseless:r_r251 n43441421 n4029666 R=10k
r_noiseless:r_r252 mid n4344090 R=1
r_noiseless:r_r253 n4362495 n4040957 R=3.43284k
r_noiseless:r_r254 n43625331 n4362495 R=10k
r_noiseless:r_r255 mid n4040957 R=1
r_noiseless:r_r32 mid claw_clamp R=1k
r_noiseless:r_r33 mid cl_clamp R=1k
r_noiseless:r_r34 n3294630 n3294626 R=10k
r_noiseless:r_r35 mid n3294626 R=1
r_noiseless:r_r36 mid n3294630 R=39.31
r_noiseless:r_r43 mid n3294682 R=1
r_noiseless:r_r46 vcc_b 0 R=1
r_noiseless:r_r47 vcc_b n2992397 R=1m
r_noiseless:r_r48 n2992397 n2992375 R=1M
r_noiseless:r_r49 n2992375 0 R=1T
r_noiseless:r_r5 mid n3294772 R=1
r_noiseless:r_r50 n2992375 n2992413 R=1M
r_noiseless:r_r51 n2992413 vee_b R=1m
r_noiseless:r_r52 vee_b 0 R=1
r_noiseless:r_r53 vcc_clp mid R=1T
r_noiseless:r_r54 n2991729 mid R=1
r_noiseless:r_r55 n2991741 n2991729 R=1m
r_noiseless:r_r56 vee_clp mid R=1T
r_noiseless:r_r57 n2991763 mid R=1
r_noiseless:r_r58 n2991765 n2991763 R=1m
r_noiseless:r_r59 n2991807 mid R=1T
r_noiseless:r_r6 n3294776 n3294772 R=100M
r_noiseless:r_r60 n2991809 mid R=1
r_noiseless:r_r61 n2991811 n2991809 R=1m
r_noiseless:r_r62 n2991831 n2991837 R=1m
r_noiseless:r_r63 n2991849 mid R=1T
r_noiseless:r_r64 n2991837 mid R=1
r_noiseless:r_r65 n2991901 mid R=1T
r_noiseless:r_r66 n2991905 mid R=1
r_noiseless:r_r67 n2991907 n2991905 R=1m
r_noiseless:r_r68 n2991925 n2991931 R=1m
r_noiseless:r_r69 n2991943 mid R=1T
r_noiseless:r_r7 mid n3294776 R=14.002k
r_noiseless:r_r70 n2991931 mid R=1
r_noiseless:r_r71 n2991969 vsense R=1m
r_noiseless:r_r72 vcc_b n2991997 R=1k
r_noiseless:r_r73 n2991997 n2992033 R=1m
r_noiseless:r_r74 n2992001 vee_b R=1k
r_noiseless:r_r75 n2992001 n2992029 R=1m
r_noiseless:r_r76 mid vcc_clp R=1k
r_noiseless:r_r77 vee_clp mid R=1k
r_noiseless:r_r78 n2992323 mid R=1
r_noiseless:r_r79 n2992299 mid R=1
r_noiseless:r_r8 n2991563 n2991555 R=1k
r_noiseless:r_r80 v11 n2992093 R=100
r_noiseless:r_r81 v12 n2992099 R=100
r_noiseless:r_r82 n2992105 mid R=1
r_noiseless:r_r83 n2992105 sw_ol_opax140 R=100
r_noiseless:r_rdummy mid n2992235 R=20k
r_noiseless:r_rs_inn "in-" esdn R=10m
r_noiseless:r_rs_inp "in+" esdp R=10m
r_noiseless:r_rx n2992235 n3294682 R=200k
r_noiseless:r_rx1 mid n2992151 R=1T
r_noiseless:r_rx2 vimon n2992151 R=100
r_noiseless:r_rx3 mid n2992163 R=1T
r_noiseless:r_rx4 vout_s n2992163 R=100
r_noiseless:r_r_cm1 esdp mid R=1T
r_noiseless:r_r_cm2 mid esdn R=1T
V_Source:v_vcm_max n2991623 vcc_b Vdc=-3.5
V_Source:v_vcm_min n2991635 vee_b Vdc=-100m
V_Source:v_v_grn n2991943 mid Vdc=-120
V_Source:v_v_grp n2991901 mid Vdc=120
V_Source:v_v_iscn n2991849 mid Vdc=-30
V_Source:v_v_iscp n2991807 mid Vdc=38
V_Source:v_v_orn n2992295 vclp Vdc=-12.1
V_Source:v_v_orp n2992331 vclp Vdc=12.1
block_dc_h1_opax140:x_h1 n2992235 out n2992151 mid
block_dc_h2_opax140:x_h2 n2992287 n2992323 v12 mid
block_dc_h3_opax140:x_h3 n2992267 n2992299 v11 mid
block_dc_s1_opax140:x_s1 n2992267 clamp n2992267 clamp
block_dc_s2_opax140:x_s2 clamp n2992287 clamp n2992287
vnse_opax140:x_u1 esdp n2991573 flw=0.1 glf=0.0224647 rnv=31.4026
clamp_amp_lo_opax140:x_u10 vcc_clp vee_clp vout_s mid n2991729 n2991763 g=1
clamp_amp_lo_opax140:x_u11 n2991807 n2991849 vimon mid n2991809 n2991837 g=1
clamp_amp_hi_opax140:x_u12 n2991901 n2991943 n2991969 mid n2991905 n2991931 g=10
ol_sense_opax140:x_u16 mid n2992105 n2992093 n2992099
clawp_opax140:x_u18 vimon mid n2991997 vcc_b
clawn_opax140:x_u19 mid vimon vee_b n2992001
esd_out_opax140:x_u21 out vcc vee
cl_src_opax140:x_u22 n2991811 n2991831 cl_clamp mid gain=1 ipos=0.48e1 ineg=-0.48e1
gr_src_opax140:x_u23 n2991907 n2991925 clamp mid gain=1 ipos=2e1 ineg=-2e1
sw_ol_opax140:x_u25 sw_ol_opax140 mid n3294626 n3294630
iq_src_opax140:x_u26 vimon mid vcc mid gain=1e-3
iq_src_opax140:x_u27 mid vimon mid vee gain=1e-3
aol_1_opax140:x_u30 n2991657 n2991619 mid n2991667 gain=1e-4 ipos=.5 ineg=-.5
aol_2_opax140:x_u31 n2991667 mid mid clamp gain=26.06e-3 ipos=0.79 ineg=-0.79
zo_src_opax140:x_u32 n3828449 mid mid n3294682 gain=181.818 ipos=16e5 ineg=-16e5
claw_src_opax140:x_u35 n2991741 n2991765 claw_clamp mid gain=1 ipos=0.24e1 ineg=-0.24e1
femt_opax140:x_u36 n2991573 mid nvrf=0.8
femt_opax140:x_u37 esdn mid nvrf=0.8
vos_drift_opax140:x_u4 n2991555 n2991573 dc=2.64e-05 pol=1 drift=3.50e-07
esd_in_opax140:x_u5 esdn esdp vcc vee
vcm_clamp_opax140:x_u6 n2991587 mid n2991643 mid n2991623 n2991635 gain=1
model r_noiseless R_Model TC1=0 TC2=0 Tnom=27
end opax140
;
define block_dc_h1_opax140 ( _node1 _node2 _node3 _node4)
SDD:h_h1 _node3 _node4 F[1,0]=-(1k*_c1)+_v1 C[1]="vh_h1"
V_Source:vh_h1 _node1 _node2 Vdc=0
end block_dc_h1_opax140
;
define block_dc_h2_opax140 ( _node1 _node2 _node3 _node4)
SDD:h_h2 _node3 _node4 F[1,0]=-(1*_c1)+_v1 C[1]="vh_h2"
V_Source:vh_h2 _node1 _node2 Vdc=0
end block_dc_h2_opax140
;
define block_dc_h3_opax140 ( _node1 _node2 _node3 _node4)
SDD:h_h3 _node3 _node4 F[1,0]=-(-1*_c1)+_v1 C[1]="vh_h3"
V_Source:vh_h3 _node1 _node2 Vdc=0
end block_dc_h3_opax140
;
define block_dc_s1_opax140 ( _node1 _node2 _node3 _node4)
spice_vswitch:s_s1 _node3 _node4 _node1 _node2 roff=1e12 ron=10m voff=0.0 von=10m
R:rs_s1 _node1 _node2 R=1G
;.model _s1 vswitch roff=1e12 ron=10m voff=0.0v von=10mv
end block_dc_s1_opax140
;
define block_dc_s2_opax140 ( _node1 _node2 _node3 _node4)
spice_vswitch:s_s2 _node3 _node4 _node1 _node2 roff=1e12 ron=10m voff=0.0 von=10m
R:rs_s2 _node1 _node2 R=1G
;.model _s2 vswitch roff=1e12 ron=10m voff=0.0v von=10mv
end block_dc_s2_opax140
;
define aol_1_opax140 ( "vc+" "vc-" "iout+" "iout-")
parameters gain=1e-4 ipos=.5 ineg=-.5
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=limit_warn(gain*_v2,vc-),ineg,ipos) I[2,0]=0
end aol_1_opax140
;
define aol_2_opax140 ( "vc+" "vc-" "iout+" "iout-")
parameters gain=26.06e-3 ipos=0.79 ineg=-0.79
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=limit_warn(gain*_v2,vc-),ineg,ipos) I[2,0]=0
end aol_2_opax140
;
define clamp_amp_hi_opax140 ( "vc+" "vc-" vin com "vo+" "vo-")
parameters g=10
SDD:gvox com "vo+" vin com vc 0 I[1,0]=(if(_v2>_v3) then (com) endif),((_v2-_v3,com))*g),0) \
I[2,0]=0 I[3,0]=0
SDD:gvo1 com "vo-" vin com vc 0 I[1,0]=(if(_v2<_v3) then (com) endif),((_v3,com)-_v2)*g),0) \
I[2,0]=0 I[3,0]=0
end clamp_amp_hi_opax140
;
define clamp_amp_lo_opax140 ( "vc+" "vc-" vin com "vo+" "vo-")
parameters g=1
SDD:gvox com "vo+" vin com vc 0 I[1,0]=(if(_v2>_v3) then (com) endif),((_v2-_v3,com))*g),0) \
I[2,0]=0 I[3,0]=0
SDD:gvo1 com "vo-" vin com vc 0 I[1,0]=(if(_v2<_v3) then (com) endif),((_v3,com)-_v2)*g),0) \
I[2,0]=0 I[3,0]=0
end clamp_amp_lo_opax140
;
define clawn_opax140 ( "vc+" "vc-" "iout+" "iout-")
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=_efunc_1((_v2,vc-))) I[2,0]=0
_efunc_1(x)=pwl(x,0,2.00e-04,15.0224,2.12e-04,22.0874,2.44e-04,26.1273,3.04e-04,26.8897,3.94e-04,27.2888,7.22e-04,28.0004,2.01e-03,30,8.00e-03)
end clawn_opax140
;
define clawp_opax140 ( "vc+" "vc-" "iout+" "iout-")
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=_efunc_2((_v2,vc-))) I[2,0]=0
_efunc_2(x)=pwl(x,0,2.00e-04,14.4043,2.03e-04,16.9314,2.17e-04,25.2708,3.33e-04,29.8195,4.06e-04,32.2202,4.64e-04,35.1264,5.96e-04,37.0217,8.45e-04,37.4007,9.77e-04,38,1.61e-03)
end clawp_opax140
;
define claw_src_opax140 ( "vc+" "vc-" "iout+" "iout-")
parameters gain=1 ipos=0.24e1 ineg=-0.24e1
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=limit_warn(gain*_v2,vc-),ineg,ipos) I[2,0]=0
end claw_src_opax140
;
define cl_src_opax140 ( "vc+" "vc-" "iout+" "iout-")
parameters gain=1 ipos=0.48e1 ineg=-0.48e1
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=limit_warn(gain*_v2,vc-),ineg,ipos) I[2,0]=0
end cl_src_opax140
;
define esd_in_opax140 ( esdn esdp vcc vee)
;.model esd_sw vswitch(ron=50 roff=1e12 von=500e-3 voff=450e-3)
spice_vswitch:s1 esdn vcc esdn vcc ron=50 roff=1e12 von=500e-3 voff=450e-3
spice_vswitch:s2 esdp vcc esdp vcc ron=50 roff=1e12 von=500e-3 voff=450e-3
spice_vswitch:s3 vee esdn vee esdn ron=50 roff=1e12 von=500e-3 voff=450e-3
spice_vswitch:s4 vee esdp vee esdp ron=50 roff=1e12 von=500e-3 voff=450e-3
end esd_in_opax140
;
define esd_out_opax140 ( out vcc vee)
;.model esd_sw vswitch(ron=50 roff=1e12 von=500e-3 voff=450e-3)
spice_vswitch:s1 out vcc out vcc ron=50 roff=1e12 von=500e-3 voff=450e-3
spice_vswitch:s2 vee out vee out ron=50 roff=1e12 von=500e-3 voff=450e-3
end esd_out_opax140
;
define femt_opax140 ( _node1 _node2)
parameters nvrf=0.8
SDD:e1 _node5 0 _node3 0 I[1,0]=0 F[2,0]=(10*_v1)-_v2
R:r1 _node5 0 R=1.184*pow(nvrf,2)
R:r2 _node5 0 R=1.184*pow(nvrf,2)
SDD:g1 _node3 0 _node1 _node2 I[1,0]=0 I[2,0]=1e-6*_v1
end femt_opax140
;
define gr_src_opax140 ( "vc+" "vc-" "iout+" "iout-")
parameters gain=1 ipos=2e1 ineg=-2e1
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=limit_warn(gain*_v2,vc-),ineg,ipos) I[2,0]=0
end gr_src_opax140
;
define iq_src_opax140 ( "vc+" "vc-" "iout+" "iout-")
parameters gain=1e-3
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=(if((_v2,vc-)<=0) endif),0,gain*_v2,vc-)) I[2,0]=0
end iq_src_opax140
;
define ol_sense_opax140 ( com "sw+" oln olp)
SDD:gswx com "sw+" oln com olp com I[1,0]=(if((_v2>10e-3||_v3>10e-3)) then (1) else (0) endif) \
I[2,0]=0 I[3,0]=0
end ol_sense_opax140
;
define sw_ol_opax140 ( sw_ol_opax140 mid cap_l cap_r)
;.model ol_sw vswitch(ron=1e-3 roff=1e12 von=900e-3 voff=800e-3)
spice_vswitch:s1 cap_l cap_r sw_ol_opax140 mid ron=1e-3 roff=1e12 von=900e-3 voff=800e-3
end sw_ol_opax140
;
define vcm_clamp_opax140 ( "vin+" "vin-" "iout-" "iout+" "vp+" "vp-")
parameters gain=1
SDD:g1 "iout+" "iout-" vin 0 vp 0 I[1,0]=limit_warn(gain*_v2,vin-),_v3,vin-),_v3,vin-)) \
I[2,0]=0 I[3,0]=0
end vcm_clamp_opax140
;
define vnse_opax140 ( _node1 _node2)
parameters flw=0.1 glf=0.0224647 rnv=31.4026
model dvn Diode Kf=pow(flw,0.5)/1e11 Is=1.0e-16 Ibv=1e-10 Tnom=27 IkModel=1 Imax=1000 Trs1=0 \
Trs2=0
I_Source:i1 0 _node7 Idc=10e-3
I_Source:i2 0 _node8 Idc=10e-3
dvn:d1 _node7 0 Mode=1
dvn:d2 _node8 0 Mode=1
SDD:e1 _node7 _node8 _node3 _node6 I[1,0]=0 F[2,0]=(glf*_v1)-_v2
R:r1 _node3 0 R=1e9
R:r2 _node3 0 R=1e9
R:r3 _node3 _node6 R=1e9
SDD:e2 _node5 0 _node6 _node4 I[1,0]=0 F[2,0]=(10*_v1)-_v2
R:r4 _node5 0 R=rnv
R:r5 _node5 0 R=rnv
R:r6 _node3 _node4 R=1e9
R:r7 _node4 0 R=1e9
SDD:e3 _node3 _node4 _node1 _node2 I[1,0]=0 F[2,0]=(1*_v1)-_v2
end vnse_opax140
;
define vos_drift_opax140 ( "vos+" "vos-")
parameters dc=2.64e-05 pol=1 drift=3.50e-07
SDD:e1 "vos+" "vos-" F[1,0]=(dc+pol*drift*(temp-27))-_v1
end vos_drift_opax140
;
define zo_src_opax140 ( "vc+" "vc-" "iout+" "iout-")
parameters gain=181.818 ipos=16e5 ineg=-16e5
SDD:g1 "iout+" "iout-" vc 0 I[1,0]=limit_warn(gain*_v2,vc-),ineg,ipos) I[2,0]=0
end zo_src_opax140
;
Kailyn Chen：
您好，有些器件提供了ADS model可以直接用，OPA140 提供的是spice model，抱歉没有关于如何将spice model导入到ADS相关指南。
我们常用的是将spice model导入到TINA中使用。 OPA140直接提供了TINA reference model，可以直接打开进行仿真。
运放使用TINA对其AC，DC传输特性，幅频特性仿真非常方面，建议使用TINA对运放进行仿真。
,
Kailyn Chen：
您好，还有其他问题吗？您还是想使ADS 进行仿真是吗？
,
Guixue L：
我需要为设计的电路仿真，进行例如输入电容等参数的评估，在其他平台好像无法实现
,
Kailyn Chen：
您好，抱歉之前未能解决您的问题。
我找到一篇如何将spice model 导入到ADS的文章以及视频，您这边参考下，看是否能解决您的问题，如不能，再反馈。
,
Guixue L：
不是导入的问题，是导入生成.net后报错
,
Kailyn Chen：
如果能正常导入，那不是Spice model的问题呢。
如果是spice model的问题我可以帮您和tools team确认。所以抱歉您的问题我这边无法帮助到您。
