TI中文支持网Part Number:SN74LVC1G00Other Parts Discussed in Thread:SN74LVC1G08, SN74LVC1G14, SN74AHC1G86,
hi:
During the test, I found that the SC70 package of TI, including AND gate, NAND gate, XOR gate, positive logic gate, NOT gate, the action level of the rising and falling edge input, did not match the DATESHEET. The rising and falling input of the AND gate, NAND gate, XOR gate are around 1.5 － 1.7; the rising input of the NOT gate is around 1.9 and its falling input is around 1.0; the rising of the positive logic gate is around 2.1 and its falling is around 0.55. Could you help me figure out what may be the cause of this phenomenon?
Other relevant models:TI\SN74LVC1G14 TI\SN74LVC1G08 TI\SN74AHC1G86(CH3:Pink,CH4:Blue)
circuit：
wave:
positive logic
XOR
NAND
AND
NOT
Amy Luo：
您好，
这里是中文论坛，您可以使用中文描述您的问题。
您说的是上述芯片可以识别的电平电压吗？下面截图是 SN74LVC1G00的电平识别范围，这个表格中的输入高电平和低电平是保证所有器件都可以识别的电平范围，对于有些器件输入高电平可能达不到下表格中的最低电压也可能会被识别为高电平，这是因为工艺问题元件个体之间会存在差异，下表格参数是对所有元件可以100%识别到的电平范围。
