TI中文支持网Part Number:CDCI6214
烧写EEPROM是按照文档操作的，代码如下
cdci6214_write_reg(0x00,0x1010);//step2. Write 1 to recal to calibrate the VCO in this operation mode
#define WRITE_EEPROM
#ifdef WRITE_EEPROM
cdci6214_write_reg(0x03,page);//step3. Select the EEPROM page,send regcommit command
cdci6214_write_reg(0x0f, 0x5037);//step4. Unlock the EEPROM for write access
cdci6214_write_reg(0x03, (1<<12)|page);//step5. Start the commit operation by writing a 1 to regcommit
usleep(600000);//wait 600ms
cdci6214_write_reg(0x03, 0x4000);//step6. Force a CRC update by writing a 1 to update_crc
cdci6214_read_reg(0x09,&nvmscrc);//step7. Read back the calculated CRC in nvmlcrc
cdci6214_write_reg(0x0d,0x3f);//step8. Store the read CRC value in the EEPROM by writing 0x3F to nvm_wr_addr
cdci6214_write_reg(0x0e, nvmscrc);//step8. and then the CRC value to nvm_wr_data.
usleep(10000);//wait 10ms
回读寄存器时发现reg07状态不对，值为0x0024,,nvmcrcerr =1,config_done=1, 但是正常应该是cal_done也要=1，lock_det=1才表示锁定呢，不知道crc错误会不会影响
cdci_regs为烧写值，regs_readback 为回读值
u32 cdci_regs[]={
0x003F4210,
0x003E4218,
0x003D1500,
0x003C0018,
0x003B1061,
0x003A0000,
0x00398851,
0x00380005,
0x00370000,
0x00360000,
0x00358000,
0x00340008,
0x00338861,
0x00320425,
0x00310006,
0x00300000,
0x002F8000,
0x002E0000,
0x002D0851,
0x002C0005,
0x002B0006,
0x002A0000,
0x00298000,
0x00280008,
0x00270851,
0x00260405,
0x00250006,
0x00240000,
0x00238000,
0x00220050,
0x00210007,
0x00200000,
0x001F1E72,
0x001E5140,
0x001D000C,
0x001C0000,
0x001B0000,
0x001A0E24,//0e1c
0x00192406,
0x00180000,
0x00170000,
0x00160000,
0x00150000,
0x00140001,
0x00130000,
0x0012FFFF,
0x001126C4,
0x0010921F,
0x000FA037,
0x000E0000,
0x000D0000,
0x000C0000,
0x000B0000,
0x000A0000,
0x00090000,
0x00080001,
0x00070C0D,
0x000619CA,
0x00050008,
0x000400F7,
0x00030000,
0x00020055,
0x00016854,
0x00001000,
};
regs_readback [64]= [0x1000, 0x6854, 0x0055, 0x0000, 0x00f7, 0x0008, 0x19ca, 0x0024, 0x0001, 0x9928, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xa037, 0x921f, 0x26c4, 0xffff, 0x0000, 0x0001, 0x0000, 0x0000, 0x0580, 0x0601, 0x0006, 0x0e24, 0x0000, 0x0000, 0x000c, 0x5140, 0x1e72, 0x0000, 0x0007, 0x0050, 0x8000, 0x0000, 0x0006, 0x0405, 0x0851, 0x0008, 0x8000, 0x0000, 0x0006, 0x0005, 0x0a51, 0x0000, 0x8000, 0x0000, 0x0006, 0x0425, 0x8861, 0x0008, 0x8000, 0x0000, 0x0000, 0x0005, 0x8a51, 0x0000, 0x1061, 0x0018, 0x1500, 0x4218, 0xc210]
xiao weihua：
the pll is configured that ref clk is 25MHz, and output 100MHz lvds
,
Amy Luo：
您好，
我看到您也将此问题发布在了E2E英文技术论坛上，如果您对此问题仍存有疑问，请跟进英文论坛工程师的回复，请资深的英文论坛工程师为您提供进一步的支持：
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1181694/cdci6214-crc?tisearch=e2e-sitesearch&keymatch=CDCI6214#
