TI中文支持网Part Number:TMS320F28062F
因为现有程序需要添加一帧接收报文，按照现有程序的配置，查看对应邮箱的使能状态为1表示邮箱已经使能。在运行中获取接收Pending标志位，发现一直不是1，表示没有收到数据。更换了5个邮箱，现象一样。
原本程序里有一个接收邮箱是能正常使用的，将两个邮箱配置接收同一帧ID，可以使用的邮箱接收正常。现在实在不清楚为什么这个邮箱不能用。
下面附上CAN相关的函数
寄存器配置函数，设置0-15为发送，16-31为接收
void CAN_setRegs(CAN_Handle canHandle)
{
CAN_Obj *can = (CAN_Obj *)canHandle;
struct ECAN_REGS ECanaShadow;
__asm(" EALLOW");
can->ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanaShadow.CANTIOC.all = can->ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
can->ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = can->ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
can->ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
/* Configure eCAN for HECC mode – (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaShadow.CANMC.all = can->ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaShadow.CANMC.bit.DBO = 1; //The data is received or transmitted least significant byte first
ECanaShadow.CANMC.bit.ABO = 1; //After the bus-off state,the module goes back automatically into bus-on state after 128*11 recessive bits have been monitored
can->ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
can->ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
can->ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
can->ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
can->ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
can->ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
can->ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = can->ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
can->ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = can->ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
/* The following block is for 80 MHz SYSCLKOUT. (40 MHz CAN module clock Bit rate = 1 Mbps
See Note at end of file. */
// 根据CAN通讯模式选择CAN波特率——————————
if((UserHdl.CanComm.Mode == CAN_COMM_MODE_USER) || \
(UserHdl.CanComm.Mode == CAN_COMM_MODE_MCUCMD))
{
//主频90MHz(1Mbps)
// ECanaShadow.CANBTC.bit.TSEG2REG = 2;
// ECanaShadow.CANBTC.bit.TSEG1REG = 10;
// ECanaShadow.CANBTC.bit.BRPREG = 2;
//主频120MHz(250Kbps)
// ECanaShadow.CANBTC.bit.TSEG2REG = 4;
// ECanaShadow.CANBTC.bit.TSEG1REG = 13;
// ECanaShadow.CANBTC.bit.BRPREG = ((USER_SYSTEM_FREQ_MHz*25)/250) – 1; //Baudrate = 2Mbps/(BRPREG+1)
//主频120MHz(1Mbps)
// ECanaShadow.CANBTC.bit.TSEG2REG = 4;
// ECanaShadow.CANBTC.bit.TSEG1REG = 13;
// ECanaShadow.CANBTC.bit.BRPREG = ((USER_SYSTEM_FREQ_MHz*25)/1000) – 1; //Baudrate = 2Mbps/(BRPREG+1)
//主频100MHz(250Kbps)
// ECanaShadow.CANBTC.bit.TSEG2REG = 4;
// ECanaShadow.CANBTC.bit.TSEG1REG = 13;
// ECanaShadow.CANBTC.bit.BRPREG = (2500 / 250) – 1; //Baudrate = 2Mbps/(BRPREG+1)
//主频90MHz(250Kbps)
ECanaShadow.CANBTC.bit.TSEG2REG = 4;
ECanaShadow.CANBTC.bit.TSEG1REG = 13;
ECanaShadow.CANBTC.bit.BRPREG = (2250 / 250) – 1; //Baudrate = 2Mbps/(BRPREG+1)
}
else
{
//主频90MHz(1Mbps)
// ECanaShadow.CANBTC.bit.TSEG2REG = 2;
// ECanaShadow.CANBTC.bit.TSEG1REG = 10;
// ECanaShadow.CANBTC.bit.BRPREG = 2;
//主频90MHz(250Kbps)
ECanaShadow.CANBTC.bit.TSEG2REG = 4;
ECanaShadow.CANBTC.bit.TSEG1REG = 13;
ECanaShadow.CANBTC.bit.BRPREG = (2250 / 250) – 1; //Baudrate = 2Mbps/(BRPREG+1)
/*
//主频120MHz(1Mbps)
ECanaShadow.CANBTC.bit.TSEG2REG = 4;
ECanaShadow.CANBTC.bit.TSEG1REG = 13;
ECanaShadow.CANBTC.bit.BRPREG = ((USER_SYSTEM_FREQ_MHz*25)/1000) – 1; //Baudrate = 2Mbps/(BRPREG+1)
*/
/*
//主频90MHz(1Mbps)
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
ECanaShadow.CANBTC.bit.BRPREG = (3000 / 1000) – 1; //Baudrate = 2Mbps/(BRPREG+1)
*/
}
//主频40MHz
/*
ECanaShadow.CANBTC.bit.TSEG2REG = 4;
ECanaShadow.CANBTC.bit.TSEG1REG = 13;
ECanaShadow.CANBTC.bit.BRPREG = (1000 / 250) – 1;//Baudrate = 2Mbps/(BRPREG+1)
*/
ECanaShadow.CANBTC.bit.SAM = 0; //The CAN module samples only once at the sampling point
can->ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = can->ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
can->ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = can->ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
can->ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
// Configure Mailboxes 0-15 as Tx, 16-31 as Rx
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
can->ECanaRegs.CANMD.all = 0xFFFF0000;
can->ECanaRegs.CANMIM.all = 0xFFFF0000;
// 1 = Mailbox interrupt is enabled
// 0 = Mailbox interrupt is disabled.
// Configure the eCAN for normal mode
// Enable the enhanced features of the eCAN.
ECanaShadow.CANMC.all = can->ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.STM = 0; // Configure CAN for normal mode
can->ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Disable all Mailboxes */
can->ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
// Mailboxs can be written to 16-bits or 32-bits at a time
// Write to the MSGID field of TRANSMIT mailboxes MBOX0 – 15
can->ECanaMboxes.MBOX0.MSGID.all = 0; //运行状态1
can->ECanaMboxes.MBOX1.MSGID.all = 0; //运行状态2
can->ECanaMboxes.MBOX2.MSGID.all = 0;
can->ECanaMboxes.MBOX3.MSGID.all = 0;
can->ECanaMboxes.MBOX4.MSGID.all = 0;
can->ECanaMboxes.MBOX5.MSGID.all = 0;
can->ECanaMboxes.MBOX6.MSGID.all = 0;
can->ECanaMboxes.MBOX7.MSGID.all = 0;
can->ECanaMboxes.MBOX8.MSGID.all = 0;
can->ECanaMboxes.MBOX9.MSGID.all = 0;
can->ECanaMboxes.MBOX10.MSGID.all = 0;
can->ECanaMboxes.MBOX11.MSGID.all = 0;
can->ECanaMboxes.MBOX12.MSGID.all = 0;
can->ECanaMboxes.MBOX13.MSGID.all = 0;
can->ECanaMboxes.MBOX14.MSGID.all = 0;
can->ECanaMboxes.MBOX15.MSGID.all = 0;
can->ECanaMboxes.MBOX0.MSGID.bit.IDE = 1; // Identifier extension bit.
can->ECanaMboxes.MBOX1.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX2.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX3.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX4.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX5.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX6.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX7.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX8.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX9.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX10.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX11.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX12.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX13.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX14.MSGID.bit.IDE = 0; //VCU通讯，标准帧格式
can->ECanaMboxes.MBOX15.MSGID.bit.IDE = 1;
// Write to the MSGID field of RECEIVE mailboxes MBOX16 – 31
can->ECanaMboxes.MBOX16.MSGID.all = 0; //控制指令1
can->ECanaMboxes.MBOX17.MSGID.all = 0;
can->ECanaMboxes.MBOX18.MSGID.all = 0;
can->ECanaMboxes.MBOX19.MSGID.all = 0;
can->ECanaMboxes.MBOX20.MSGID.all = 0;
can->ECanaMboxes.MBOX21.MSGID.all = 0;
can->ECanaMboxes.MBOX22.MSGID.all = 0;
can->ECanaMboxes.MBOX23.MSGID.all = 0;
can->ECanaMboxes.MBOX24.MSGID.all = 0;
can->ECanaMboxes.MBOX25.MSGID.all = 0;
can->ECanaMboxes.MBOX26.MSGID.all = 0;
can->ECanaMboxes.MBOX27.MSGID.all = 0;
can->ECanaMboxes.MBOX28.MSGID.all = 0;
can->ECanaMboxes.MBOX29.MSGID.all = 0;
can->ECanaMboxes.MBOX30.MSGID.all = 0;
can->ECanaMboxes.MBOX31.MSGID.all = 0;
can->ECanaMboxes.MBOX16.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX17.MSGID.bit.IDE = 0; //VCU通讯，标准帧格式
can->ECanaMboxes.MBOX18.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX19.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX20.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX21.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX22.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX23.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX24.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX25.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX26.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX27.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX28.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX29.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX30.MSGID.bit.IDE = 1;
can->ECanaMboxes.MBOX31.MSGID.bit.IDE = 1;
// Specify that 8 bits will be sent/received
can->ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
can->ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;
// Write to the mailbox RAM field of MBOX0 – 15
can->ECanaMboxes.MBOX1.MDL.all = 0;
can->ECanaMboxes.MBOX1.MDH.all = 0;
can->ECanaMboxes.MBOX2.MDL.all = 0;
can->ECanaMboxes.MBOX2.MDH.all = 0;
can->ECanaMboxes.MBOX3.MDL.all = 0;
can->ECanaMboxes.MBOX3.MDH.all = 0;
can->ECanaMboxes.MBOX4.MDL.all = 0;
can->ECanaMboxes.MBOX4.MDH.all = 0;
can->ECanaMboxes.MBOX5.MDL.all = 0;
can->ECanaMboxes.MBOX5.MDH.all = 0;
can->ECanaMboxes.MBOX6.MDL.all = 0;
can->ECanaMboxes.MBOX6.MDH.all = 0;
can->ECanaMboxes.MBOX7.MDL.all = 0;
can->ECanaMboxes.MBOX7.MDH.all = 0;
can->ECanaMboxes.MBOX8.MDL.all = 0;
can->ECanaMboxes.MBOX8.MDH.all = 0;
can->ECanaMboxes.MBOX9.MDL.all = 0;
can->ECanaMboxes.MBOX9.MDH.all = 0;
can->ECanaMboxes.MBOX10.MDL.all = 0;
can->ECanaMboxes.MBOX10.MDH.all = 0;
can->ECanaMboxes.MBOX11.MDL.all = 0;
can->ECanaMboxes.MBOX11.MDH.all = 0;
can->ECanaMboxes.MBOX12.MDL.all = 0;
can->ECanaMboxes.MBOX12.MDH.all = 0;
can->ECanaMboxes.MBOX13.MDL.all = 0;
can->ECanaMboxes.MBOX13.MDH.all = 0;
can->ECanaMboxes.MBOX14.MDL.all = 0;
can->ECanaMboxes.MBOX14.MDH.all = 0;
can->ECanaMboxes.MBOX15.MDL.all = 0;
can->ECanaMboxes.MBOX15.MDH.all = 0;
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
// The identifier extension bit stored in the mailbox determines which messages shall be received.
// Received identifier bit value must match the corresponding identifier bit of the MSGID register.
can->ECanaLAMRegs.LAM16.all = 0;
can->ECanaLAMRegs.LAM17.all = 0;
can->ECanaLAMRegs.LAM18.all = 0;
can->ECanaLAMRegs.LAM19.all = 0;
can->ECanaLAMRegs.LAM20.all = 0;
can->ECanaLAMRegs.LAM21.all = 0;
can->ECanaLAMRegs.LAM22.all = 0;
can->ECanaLAMRegs.LAM23.all = 0;
can->ECanaLAMRegs.LAM24.all = 0;
can->ECanaLAMRegs.LAM25.all = 0;
can->ECanaLAMRegs.LAM26.all = 0;
can->ECanaLAMRegs.LAM27.all = 0;
can->ECanaLAMRegs.LAM28.all = 0;
can->ECanaLAMRegs.LAM29.all = 0;
can->ECanaLAMRegs.LAM30.all = 0;
can->ECanaLAMRegs.LAM31.all = 0;
// Enable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
// can->ECanaRegs.CANME.all = 0x80018003; //Id设置子函数中使能邮箱
// disable ecan interrupt
can->ECanaRegs.CANGIM.bit.GIL = 0; //All global interrupts are mapped to the ECAN0INT interrupt line.
can->ECanaRegs.CANGIM.bit.I0EN = 0; //disables all interrupts for the ECAN0INT line if the corresponding masks are set.
can->ECanaRegs.CANGIM.bit.I1EN = 0; //ECAN1INT interrupt line is disabled.
can->ECanaRegs.CANMIM.all = 0x00000000; // Mailbox interrupt is enabled if a message has been received without any error
can->ECanaRegs.CANMIL.all = 0x00000000; // mailbox interrupt is generated on interrupt line 0.
__asm(" EDIS");
return;
} // end of ADC_setSampleOverlapMode() function
这个是设置ID的函数，为通用设置函数
void CAN_SetId(CAN_Handle canHandle, uint32_t Id, uint16_t box, uint16_t Id_ext)
{
CAN_Obj *can = (CAN_Obj *)canHandle;
if(32 > box) //Box0
{
can->ECanaRegs.CANME.all &= (~(0x00000001 << box)); // Required before writing the MSGIDs
uint32_t *CanIdPnt;
CanIdPnt = (uint32_t *)&(can->ECanaMboxes.MBOX0.MSGID.all);
CanIdPnt += (box * 4);
if(Id_ext == 1)
{
*CanIdPnt = (Id & 0x1FFFFFFF) | 0x80000000;
}
else
{
*CanIdPnt = (Id & 0x1FFFFFFF) | 0x00000000;
}
can->ECanaRegs.CANME.all |= ((0x00000001 << box)); // Required before writing the MSGIDs
}
return;
}
这个是接收函数，先前的工程师设置为需要哪个邮箱再这个函数中加入哪个邮箱的接收。31号为可以使用的邮箱，18号是有问题的邮箱
uint16_t CAN_RxData(CAN_Handle canHandle, uint16_t *data, uint16_t box)
{
CAN_Obj *can = (CAN_Obj *)canHandle;
if(16 == box)
{
if(can->ECanaRegs.CANRMP.bit.RMP16) //Box16
{
can->ECanaRegs.CANRMP.bit.RMP16 = 1; //Clear
*data = can->ECanaMboxes.MBOX16.MDL.word.LOW_WORD;
*(data+1) = can->ECanaMboxes.MBOX16.MDL.word.HI_WORD;
*(data+2) = can->ECanaMboxes.MBOX16.MDH.word.LOW_WORD;
*(data+3) = can->ECanaMboxes.MBOX16.MDH.word.HI_WORD;
return 1;
}
else
{
return 0;
}
}
else if(31 == box)
{
if(can->ECanaRegs.CANRMP.bit.RMP31) //Box31
{
can->ECanaRegs.CANRMP.bit.RMP31 = 1; //Clear
*data = can->ECanaMboxes.MBOX31.MDL.word.LOW_WORD;
*(data+1) = can->ECanaMboxes.MBOX31.MDL.word.HI_WORD;
*(data+2) = can->ECanaMboxes.MBOX31.MDH.word.LOW_WORD;
*(data+3) = can->ECanaMboxes.MBOX31.MDH.word.HI_WORD;
return 1;
}
else
{
return 0;
}
}
else if(17 == box)
{
if(can->ECanaRegs.CANRMP.bit.RMP17) //Box17
{
can->ECanaRegs.CANRMP.bit.RMP17 = 1; //Clear
*data = can->ECanaMboxes.MBOX17.MDL.word.LOW_WORD;
*(data+1) = can->ECanaMboxes.MBOX17.MDL.word.HI_WORD;
*(data+2) = can->ECanaMboxes.MBOX17.MDH.word.LOW_WORD;
*(data+3) = can->ECanaMboxes.MBOX17.MDH.word.HI_WORD;
return 1;
}
else
{
return 0;
}
}
#if CTRL_Board == CTRL_Board_03XB
else if(18 == box)
{
UserHdl.CanComm.flag_6010_test = 1;
if(can->ECanaRegs.CANRMP.bit.RMP18) //Box20
{
UserHdl.CanComm.flag_6010_test = 2;
can->ECanaRegs.CANRMP.bit.RMP18 = 1; //Clear
*data = can->ECanaMboxes.MBOX18.MDL.word.LOW_WORD;
*(data+1) = can->ECanaMboxes.MBOX18.MDL.word.HI_WORD;
*(data+2) = can->ECanaMboxes.MBOX18.MDH.word.LOW_WORD;
*(data+3) = can->ECanaMboxes.MBOX18.MDH.word.HI_WORD;
UserHdl.CanComm.flag_6010_test = 3;
return 1;
}
else
{
// UserHdl.CanComm.flag_6010_test = 4;
return 0;
}
}
#endif
else
{
return 0;
}
}
pengxiang wang：
现在问题更新了，原来pending不置1是因为邮箱box设置的时候一个32位的数据与一个16位数据移位结果为0，使得18号邮箱没能正确设置ID，没有收到那个ID自然没有pending标志位。（但是我心中仍然有疑惑，18号移位错误，31号却正常？？？）
然后呢，现在查看寄存器的结果，ID设置正确，邮箱使能完毕，Pending标志位能够正常置1，结果数据不会转移。这里逻辑很简单，判断18号pending为1，进入内部将邮箱的数据转移给数组。查看寄存器对应的pending是1，结果就是进不去。设置的flag_6010_test监控量，在if以外会变成18，只要进去if就会被置3。结果就一直是18。怀疑是外部监控pending是1没错，但是到执行数据转移的时候被清零了。有没有什么排查方法？
,
Cherry Zhou：
您好，
和您确认下，您目前的问题如下对吗？
pengxiang wang 说：
原来pending不置1是因为邮箱box设置的时候一个32位的数据与一个16位数据移位结果为0，使得18号邮箱没能正确设置ID，没有收到那个ID自然没有pending标志位。（但是我心中仍然有疑惑，18号移位错误，31号却正常？？？）
然后呢，现在查看寄存器的结果，ID设置正确，邮箱使能完毕，Pending标志位能够正常置1，结果数据不会转移。这里逻辑很简单，判断18号pending为1，进入内部将邮箱的数据转移给数组。查看寄存器对应的pending是1，结果就是进不去。设置的flag_6010_test监控量，在if以外会变成18，只要进去if就会被置3。结果就一直是18。怀疑是外部监控pending是1没错，但是到执行数据转移的时候被清零了。有没有什么排查方法？
,
pengxiang wang：
是滴。可以看一下我截的图。查看寄存器确实Pending已经是1了，但是接收函数中的判断条件却进不去。
,
Cherry Zhou：
好的，我们把问题升级到英文论坛咨询下资深的工程师哈，有答复尽快回复您。
,
Cherry Zhou：
您好，
看起来是因为没有跟随32位读取/写入。对 eCAN 寄存器的所有读取和写入必须为32位。这一点已在 www.ti.com/SPRA876 中进行了说明。问题应该出在“if”语句中，该语句没有进行32位的读操作。将其转换为32位读取应该可以解决该问题。
