TI中文支持网您好，
请问随机LOCK的机制条件是什么呢?
DS92LV1212 的Datasheet有说明但是看不太明白，因為目前LOCK訊號會隨機發送(時間不固定)，因为目前LOCK讯号会随机发送(时间不固定)，所以想了解DS92LV1212 的工作原理，劳烦了解的人回覆一下，感谢。
Features:
Clock recovery without SYNC patterns-random lock
Random Lock Initialization and Resynchronization:
The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer, however, the DS92LV1212 can attain lock to a data stream without requiring special SYNC patterns to be sent by the Serializer.
This allows the DS92LV1212 to be used in applications where the Deserializer must operate “open-loop” and supports hot insertion into a running backplane. Because the data stream is essentially random the time for the DS92LV1212 to attain lock is variable and cannot be predicted. The primary constraint on the “random” lock time is the initial phase relation when the Deserializer is powered up. The data contained in the data stream can also affect lock time.
Typical lock times for random data have a mean of 570us and a max of 4.9ms.
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另外这段RCLK是说会参考ROUT讯号输出?
Data Transfer:
RCLK pin is the reference to data on the ROUT0-ROUT9 pins. The polarity of the RCLK edge is controlled by the RCLK_R/F input.
ROUT(0-9), LOCK and RCLK outputs will drive a minimum of three CMOS input gates (15 pF load) with 40 MHz clock.
WU YH：
不知道为什么，我选择在接口论坛发布，但是发布在仿真、硬件和系统设计工具论坛上，
如果有需要迁移请告知我，谢谢
,
Amy Luo：
您好，
DS92LV1212 应该是已经停产了，我在TI官网找不到关于它的任何信息。对于停产的产品，非常抱歉，TI不再提供支持。
