28335 死区配置

1. 28335配置如下做特定消谐程序，脉冲边沿的修改在中断中进行，在这种配置下可以发出有死区的脉冲，但死区电平不是想要的， 若修改EPwm1Regs.DBCTL.bit.POLSEL = 2或0，则输出脉冲被置低。
     请问28335死区配置有什么特殊要求吗？

   // Setup TBCLK    EPwm1Regs.TBPRD = 16667;                    // Set timer period   EPwm1Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
    // Set Compare values
   EPwm1Regs.CMPA.half.CMPA = 0;     // Set compare A value
   EPwm1Regs.CMPB = 0;               // Set Compare B value
     // Setup counter mode
   EPwm1Regs.TBCTL.bit.CTRMODE = 0;   // Count up
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;     // Disable phase loading
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;          // Clock ratio to SYSCLKOUT 30M
   EPwm1Regs.TBCTL.bit.CLKDIV = 0;             //

   // Setup shadowing
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;    // Load on CTR = Zero
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; 

   // Set actions
   EPwm1Regs.AQCTLA.all = 0;                 EPwm1Regs.AQCTLB.all = 0;

   // Interrupt where we will change the Compare Values
   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;      // Select INT on Zero event
   EPwm1Regs.ETSEL.bit.INTEN = 1;                 // Enable INT
   EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;            // Generate INT on 1st event 

   // DeadTime control
   EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
   EPwm1Regs.DBCTL.bit.POLSEL = 1;                   //   EPwm1Regs.DBCTL.bit.OUT_MODE = 2;    // Dead-band generation is enabled

   // DeadTime   EPwm1Regs.DBRED = DeadTime;                   // Rising Edge Delay Count 10-bit counter
   EPwm1Regs.DBFED = DeadTime;                   // Falling Edge Delay Count 10-bit counter
     EPwm1Regs.AQSFRC.bit.RLDCSF=3;

2.AQCSFRC寄存器问题
     AQCSFRC寄存器的CSFA和CSFB  datasheet中说配置为1强制低，配置为2强制高，但CSFA的配置结果与实际测试相反，我用这个寄存器做PDP保护，不知道怎么解释？
  

user1289146：

回复 Johnson Chen1:

谢谢Johnson Chen1 .

我用的是三相半桥,高有效,死区的四种配置,我只有低有效互补这种模式时可以发出PWM脉冲(死区重叠部分为高,不满足要求),若死区配置为高有效互补或低有效 则没有PWM脉冲输出.  不知道为什么?

1. 28335配置如下做特定消谐程序，脉冲边沿的修改在中断中进行，在这种配置下可以发出有死区的脉冲，但死区电平不是想要的， 若修改EPwm1Regs.DBCTL.bit.POLSEL = 2或0，则输出脉冲被置低。
     请问28335死区配置有什么特殊要求吗？

   // Setup TBCLK    EPwm1Regs.TBPRD = 16667;                    // Set timer period   EPwm1Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
    // Set Compare values
   EPwm1Regs.CMPA.half.CMPA = 0;     // Set compare A value
   EPwm1Regs.CMPB = 0;               // Set Compare B value
     // Setup counter mode
   EPwm1Regs.TBCTL.bit.CTRMODE = 0;   // Count up
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;     // Disable phase loading
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;          // Clock ratio to SYSCLKOUT 30M
   EPwm1Regs.TBCTL.bit.CLKDIV = 0;             //

   // Setup shadowing
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;    // Load on CTR = Zero
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; 

   // Set actions
   EPwm1Regs.AQCTLA.all = 0;                 EPwm1Regs.AQCTLB.all = 0;

   // Interrupt where we will change the Compare Values
   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;      // Select INT on Zero event
   EPwm1Regs.ETSEL.bit.INTEN = 1;                 // Enable INT
   EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;            // Generate INT on 1st event 

   // DeadTime control
   EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
   EPwm1Regs.DBCTL.bit.POLSEL = 1;                   //   EPwm1Regs.DBCTL.bit.OUT_MODE = 2;    // Dead-band generation is enabled

   // DeadTime   EPwm1Regs.DBRED = DeadTime;                   // Rising Edge Delay Count 10-bit counter
   EPwm1Regs.DBFED = DeadTime;                   // Falling Edge Delay Count 10-bit counter
     EPwm1Regs.AQSFRC.bit.RLDCSF=3;

2.AQCSFRC寄存器问题
     AQCSFRC寄存器的CSFA和CSFB  datasheet中说配置为1强制低，配置为2强制高，但CSFA的配置结果与实际测试相反，我用这个寄存器做PDP保护，不知道怎么解释？
  

user1289146：

回复 user1289146:

死区问题解决，我的笔记本电脑出问题了！  换台电脑搞定！