TI中文支持网Part Number:TMS320C6678
TI技术专家您好，C6678的DDR3部分基板管教延时数据能否发一份？同时请问下两个问题：
1.PCB是否需要加管脚延时呢？
2.DDR3初始化不过，我们硬件上边接在PTV15脚上的电阻是1%的44.2Ω，我在其中5块板上配置DDR_TERM为RZQ/6没问题，但是有一块不行，配成RZQ/4就OK了。除了此处电阻还有什么会导致此类现象呢？
谢谢。
Nancy Wang：
1、不需要知道该信息，严格按照TI提供的布线规则即可。
www.ti.com/…/spracl8.pdf
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/990384/66ak2g12-keystone-ii-66ak2g12aby100-pin-delay-values
2、除了硬件部分需要严格按照TI手册要求之外，还需要做leveling来优化读写时序。
www.ti.com.cn/…/sprabl2e.pdf
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jj jj：
请问ti工程师，您说的leveling，是指的6678 ddr控制器的硬件自动leveling吗？ 像AM335X，需要进行software leveling，是因为此类芯片不支持硬件leveling吗？
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jj jj：
请问ti工程师，您说的leveling，是指的6678 ddr控制器的硬件自动leveling吗？ 像AM335X，需要进行software leveling，是因为此类芯片不支持硬件leveling吗？
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Nancy Wang：
是software leveling。
为了保证DDR3的信号完整性，优化相关的读写时序参数，匹配不同板子因板材、layout走线、线宽等多种因素可能会造成的阻抗变化，所以要求，DDR3的设计，必须要进行Software Leveling，获得最适应于当前layout的DDR3 PHY读写参数。
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jj jj：
如果叫softleveling的话，还请麻烦再继续解答下我的疑惑：
根据ti pdk库下提供的示例程序关于ddr3初始化接口：
void ddr3_setup_auto_lvl_1333(){ //int i,TEMP,startlo, stoplo,starthi, stophi; int TEMP; KICK0 = KICK0_UNLOCK; KICK1 = KICK1_UNLOCK;
/* Wait for PLL to lock = min 500 ref clock cycles. With refclk = 100MHz, = 5000 ns = 5us */ sleep_timer(1000);
/***************** 3.2 DDR3 PLL Configuration ************/ /* Done before */
/**************** 3.0 Leveling Register Configuration ********************/ /* Using partial automatic leveling due to errata */
/**************** 3.3 Leveling register configuration ********************/ DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100 DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1 DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
//From 4.2.1 Executing Partial Automatic Leveling — Start DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS //From 4.2.1 Executing Partial Automatic Leveling — End
//Values with invertclkout = 1 /**************** 3.3 Partial Automatic Leveling ********************/ /*DATA0_WRLVL_INIT_RATIO = 0x78; DATA1_WRLVL_INIT_RATIO = 0x76; DATA2_WRLVL_INIT_RATIO = 0x72; DATA3_WRLVL_INIT_RATIO = 0x76; DATA4_WRLVL_INIT_RATIO = 0x69; DATA5_WRLVL_INIT_RATIO = 0x69; DATA6_WRLVL_INIT_RATIO = 0x5B; DATA7_WRLVL_INIT_RATIO = 0x60; DATA8_WRLVL_INIT_RATIO = 0x00;
DATA0_GTLVL_INIT_RATIO = 0xAF; DATA1_GTLVL_INIT_RATIO = 0xB1; DATA2_GTLVL_INIT_RATIO = 0xA3; DATA3_GTLVL_INIT_RATIO = 0xA0; DATA4_GTLVL_INIT_RATIO = 0x9B; DATA5_GTLVL_INIT_RATIO = 0x9B; DATA6_GTLVL_INIT_RATIO = 0x98; DATA7_GTLVL_INIT_RATIO = 0x92; DATA8_GTLVL_INIT_RATIO = 0x00; */
//Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 DDR_DDRPHYC &= ~(0x00008000); DDR_DDRPHYC |= (0x00008000); DDR_DDRPHYC &= ~(0x00008000);
/***************** 3.4 Basic Controller and DRAM Configuration ************/ DDR_SDRFC = 0x0000c34; // enable configuration
/* DDR_SDTIM1 = 0x1113783C; */ TEMP = 0; TEMP |= 0x8 << 25; // T_RP bit field 28:25 TEMP |= 0x8 << 21; // T_RCD bit field 24:21 TEMP |= 0x9 << 17; // T_WR bit field 20:17 TEMP |= 0x17 << 12; // T_RAS bit field 16:12 TEMP |= 0x20 << 6; // T_RC bit field 11:6 TEMP |= 0x7 << 3; // T_RRD bit field 5:3 TEMP |= 0x4; // T_WTR bit field 2:0 DDR_SDTIM1 = 0x0AAAE4E2; //TEMP;
/* DDR_SDTIM2 = 0x30717FE3; */ TEMP = 0; TEMP |= 0x3 << 28; // T_XP bit field 30:28 TEMP |= 0x71 << 16; // T_XSNR bit field 24:16 TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6 TEMP |= 0x4 << 3; // T_RTP bit field 5:3 TEMP |= 0x3; // T_CKE bit field 2:0 DDR_SDTIM2 = 0x206B7FDA;//TEMP;
/* DDR_SDTIM3 = 0x559F86AF; */ TEMP = 0; TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value) TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value) TEMP |= 0x4 << 21; // T_CKESR bit field 23:21 TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15 TEMP |= 0x6a << 4; // T_RFC bit field 12:4 TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value) DDR_SDTIM3 = 0x557F867F; //TEMP;
DDR_DDRPHYC = 0x0010010F;
DDR_ZQCFG = 0x70073214;
DDR_PMCTL = 0x0;
DDR_SDRFC = 0x0000c34; // enable configuration
/* DDR_SDCFG = 0x63062A32; */ /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32; // last config write DRAM init occurs */ TEMP = 0; TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value) TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27 TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24 TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21 TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18 TEMP |= 0x2 << 16; // CWL bit field 17:16 TEMP |= 0x0 << 14; // NM bit field 15:14 TEMP |= 0xA << 10; // CL bit field 13:10 TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7 TEMP |= 0x3 << 4; // IBANK bit field 6:4 TEMP |= 0x0 << 3; // EBANK bit field 3:3 TEMP |= 0x2; // PAGESIZE bit field 2:0 DDR_SDCFG = 0x63072B33;//TEMP;
//Wait 600us for HW init to complete sleep_timer(100000);
DDR_SDRFC = 0x0000c34; //0x00001450; //Refresh rate = (7.8*666MHz)
/**************** 4.2.1 Executing Partial Automatic Leveling ********************/
DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling – This ignores read DQS leveling result and uses ratio forced value
//(0x34) instead //Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms. //Actual time = ~10-15 ms sleep_timer(100000); //GEL_TextOut("\nDDR3 initialization is complete.\n");}
以上代码 哪一部分是softleveling？ 我查阅手册，上序代码中，“4.2.1 Executing Partial Automatic Leveling ”部分是关于硬件leveling的启动；
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Nancy Wang：
software leveling就是根据前面链接中的表格获取获得最适应于当前layout的DDR3 PHY读写参数，并修改代码中的值。
